An FPGA implementation for a high throughput adaptive filter using distributed arithmetic

被引：11

作者：

Allred, DJ ^{[1
]}

Huang, W ^{[1
]}

Krishnan, V ^{[1
]}

Yoo, H ^{[1
]}

Anderson, DV ^{[1
]}

机构：

[1] Georgia Inst Technol, Atlanta, GA 30332 USA

来源：

12TH ANNUAL IEEE SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES, PROCEEDINGS | 2004年

关键词：

D O I：

10.1109/FCCM.2004.15

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper an FIR adaptive filter implementation using a multiplier-free architecture is presented. The implementation is based on distributed arithmetic (DA) which substitutes multiply-and-accumulate operations with a series of look-up-table (LUT) accesses. This can be achieved at the cost of a moderate increase in memory usage. The proposed design performs an LMS-type adaptation on a sample-by-sample basis. This is accomplished by an innovative LUT update using a matched auxiliary LUT I he system is implemented on an FPGA that enables rapid prototyping of digital circuits. Implementation results are provided to demonstrate that a high-speed LMS adaptive filter can be realized employing the proposed architecture.

引用

页码：324 / 325

页数：2