A simulation model to characterize the photolithography process of a semiconductor wafer fabrication

被引:13
作者
Arisha, A [1 ]
Young, P [1 ]
El Baradie, M [1 ]
机构
[1] Dublin City Univ, Sch Mech & Mfg Engn, Dublin 9, Ireland
关键词
photolithography process; simulation; semiconductor manufacturing;
D O I
10.1016/j.jmatprotec.2004.04.387
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
The pressures on semiconductor manufacturers due to cost considerations, rapid growth of process technology, quality constraints, feature size reduction and increasingly complex products are requiring ever higher efficiency from manuacturing facilities. The complexity of manufacturing high capacity semiconductor devices means that it is impossible to analyze the process control parameters and the production configurations using traditional analytical models. There is, therefore, ail increasing need for effective models of each manufacturing process. characterizing and analyzing the process in detail, allowing the effect of changes in the production environment oil the process to be predicted. The photolithography process is one of the most complex processes in semiconductor manufacturing. Using state-of-the-art computer simulation and a structured modeling methodology a generic model of photolithography flexible manufacturing cells has been developed and used to mimic the actual performance of the tools. Comparison of the output from the model with data from the plant shows the quality of the model. This paper discusses the technique used to develop the Simulation model and includes a details oil the structured modeling approach employed to develop reusable generic model for optimizing photolithography process parameters. (C) 2004 Elsevier B.V. All rights reserved.
引用
收藏
页码:2071 / 2079
页数:9
相关论文
共 13 条
[1]  
ARISHA A, 2003, THESIS DUBLIN CITY U
[2]  
Banks J, 2000, P WINT SIM C
[3]  
DICKENS C, 1994, TALE 2 CITIES, pCH1
[4]  
DONIAVI A, 1999, THESIS U BATH UK
[5]  
HAINES LA, 1990, IEEE P NAT AER EL C, V2, P806
[6]  
HILTON C, 1998, INTEL TECHNOL J
[7]   Production planning in semiconductor wafer fab considering variable cycle times [J].
Lee, Y ;
Kim, S ;
Yea, S ;
Kim, B .
COMPUTERS & INDUSTRIAL ENGINEERING, 1997, 33 (3-4) :713-716
[8]  
Nayani N, 1998, 1998 WINTER SIMULATION CONFERENCE PROCEEDINGS, VOLS 1 AND 2, P1017, DOI 10.1109/WSC.1998.745835
[9]   Quantifying the benefits of cycle time reduction in semiconductor wafer fabrication [J].
Nemoto, K ;
Akcali, E ;
Uzsoy, RM .
IEEE TRANSACTIONS ON ELECTRONICS PACKAGING MANUFACTURING, 2000, 23 (01) :39-47
[10]  
Phadke M.S., 1995, QUALITY ENG USING RO