Machine Learning Aided Design Optimization for Micro-chip Reliability Improvement

Micro-chip reliability keeps attracting the attention of researchers especially to the fine-pitch chip packaging where large stress concentration occurs to cause complex reliability issues. We developed a Finite Element Analysis (FEA) model to perform a parametric study to investigate the impact of multiple design parameters on chip reliability. A machine learning model has been further developed based on the FEA simulation results to make reliability prediction for chip package designs with improved computational efficiency. Multiple machine learning algorithms have been examined to identify the most suitable algorithm for chip package design optimization. Our study found that the chip dimensions have a significant impact on chip reliability and the Artificial Neural Network model is the most suitable for conducting design optimizations.