High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies

被引：51

作者：

Allam, MW ^{[1
]}

Anis, MH ^{[1
]}

Elmasry, MI ^{[1
]}

机构：

[1] Univ Waterloo, VLSI Res Grp, Waterloo, ON N2L 3G1, Canada

来源：

ISLPED '00: PROCEEDINGS OF THE 2000 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN | 2000年

关键词：

D O I：

10.1109/LPE.2000.876774

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A new high-speed Domino circuit, called HS-Domino is developed. HS-Domino resolves the trade-off between performance and noise margins in conventional CD-Domino logic while dissipating low dynamic power with minimal area overhead. A dual-threshold (MTCMOS) implementation of HS-Domino and DDCVS logic is also devised. This implementation achieves low leakage values during standby, while maintaining high performance and low dynamic power during the active mode.

引用

页码：155 / 160

页数：6

共 6 条

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