A HIGH-PERFORMANCE ARCHITECTURE OF JPEG2000 ENCODER

被引：0

作者：

Modrzyk, Damian ^{[1
]}

Staworko, Michal

机构：

[1] Evatronix SA, Integrated Circuits Dev Dept, Gliwice, Poland

来源：

19TH EUROPEAN SIGNAL PROCESSING CONFERENCE (EUSIPCO-2011) | 2011年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This article presents hardware architecture of JPEG2000 encoder core, oriented for HD video broadcast and surveillance applications. Thanks to developed efficient 2-D DWT engine that is capable of computing four coefficients per clock cycle, and adopted two EBCOT TIER-1 modules, with smart switching of the channels, the maximum compression speed of 180 Msamples/s at 100 MHz, in lossy mode is achieved. The architecture is implemented in VHDL and synthesised for FPGA devices, and ASIC 0.13 pm CMOS technology. Performance simulations, conducted on a set of natural images and video sequences, have revealed that the encoder is capable of processing 1080p 4:4:4 signal with a speed of 30 frames per second. Additionally, an excellent quality of reconstructed images has been observed, with respect to the reference, software encoder.

引用

页码：569 / 573

页数：5

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