The impact of NoC reuse on the testing of core-based systems

被引：54

作者：

Cota, E ^{[1
]}

Kreutz, M ^{[1
]}

Zeferino, CA ^{[1
]}

Carro, L ^{[1
]}

Lubaszewski, M ^{[1
]}

Susin, A ^{[1
]}

机构：

[1] Univ Fed Rio Grande do Sul, Inst Informat, PPGC, Porto Alegre, RS, Brazil

来源：

21ST IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS | 2003年

关键词：

D O I：

10.1109/VTEST.2003.1197643

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The authors propose the reuse of on-chip networks for the test of core-based systems that use this platform. Two possibilities of reuse are proposed and discussed with respect to test time minimization. An algorithm exploiting network characteristics to reduce test time is presented. Experimental results show that the parallelization capability of the network can be exploited to reduce the system test time, whereas area and pin overhead are strongly minimized.

引用

页码：128 / 133

页数：6

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