A new capacitorless 1T DRAM cell: Surrounding gate MOSFET with vertical channel (SGVC cell)

被引：40

作者：

Jeong, Hoon ^{[1
]}

Song, Ki-Whan

Park, Il Han

Kim, Tae-Hun

Lee, Yeun Seung

Kim, Seong-Goo

Seo, Jun

Cho, Kyoungyong

Lee, Kankyoon

Shin, Hyungcheol

Lee, Jong Duk

Park, Byung-Gook

机构：

[1] Seoul Natl Univ, Sch Elect Engn, Seoul 151742, South Korea

[2] Samsung Elect Co Ltd, Semicond R&D Div, ATD Team, Yongin 449711, South Korea

[3] Samsung Elect Co Ltd, Semicond R&D Div, Technol Dev Team, Yongin 449711, South Korea

[4] Samsung Elect Co Ltd, Semicond R&D Div, Proc Dev Team, Yongin 449711, South Korea

来源：

IEEE TRANSACTIONS ON NANOTECHNOLOGY | 2007年 / 6卷 / 03期

关键词：

memory effect; 1T DRAM cell; sensing margin; surrounding gate; vertical channel;

D O I：

10.1109/TNANO.2007.893575

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We propose a surrounding gate. MOSFET with vertical channel (SGVC cell) as a 1T DRAM cell. To confirm the memory operation of the SGVC cell, we simulated its memory effect and fabricated the highly scalable SGVC cell. According to simulation and measurement results, the SGVC cell can operate as a 1T DRAM having-a sufficiently large sensing margin. Also, due to its vertical channel structure and common source architecture, it can readily be made into a 4F(2) cell array.

引用

页码：352 / 357

页数：6

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