Fast and scalable lock methods for video coding on many-core architecture

被引:3
|
作者
Xu, Weizhi [2 ,6 ]
Yu, Hui [3 ]
Lu, Dianjie [4 ]
Song, Fenglong [2 ]
Wang, Da [2 ]
Ye, Xiaochun [2 ]
Pei, Songwei [5 ]
Fan, Dongrui [2 ]
Xie, Hongtao [1 ]
机构
[1] Chinese Acad Sci, Inst Informat Engn, Natl Engn Lab Informat Secur Technol, Beijing, Peoples R China
[2] Tsinghua Univ, Inst Microelect, Beijing 100084, Peoples R China
[3] Chinese Acad Sci, Inst Comp Technol, Key Lab Intelligent Informat Proc, Beijing, Peoples R China
[4] Shandong Normal Univ, Sch Informat Sci & Engn, Jinan, Peoples R China
[5] Beijing Univ Chem Technol, Dept Comp Sci & Technol, Beijing 100029, Peoples R China
[6] Chinese Acad Sci, Inst Comp Technol, State Key Lab Comp Architecture, Beijing, Peoples R China
关键词
Many-core; Hardware lock; Centralized lock; Distributed lock; Micro-benchmarks; Godson-T; Software lock; Single-core processor; SHARED-MEMORY MULTIPROCESSORS; HIGHLY PARALLEL FRAMEWORK; DEBLOCKING FILTER; HEVC; SYNCHRONIZATION; ALGORITHMS; PROCESSOR; PLATFORM;
D O I
10.1016/j.jvcir.2014.06.009
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Many-core processors are good candidates for speeding up video coding because the parallelism of these applications can be exploited more efficiently by the many-core architecture. Lock methods are important for many-core architecture to ensure correct execution of the program and communication between threads on chip. The efficiency of lock method is critical to overall performance of chipped many-core processor. In this paper, we propose two types of hardware locks for on-chip many-core architecture, a centralized lock and a distributed lock. First, we design the architectures of centralized lock and distributed lock to implement the two hardware lock methods. Then, we evaluate the performance of the two hardware locks and a software lock by quantitative evaluation micro-benchmarks on a many-core processor simulator Godson-T. The experimental results show that the locks with dedicated hardware support have higher performance than the software lock, and the distributed hardware lock is more scalable than the centralized hardware lock. (C) 2014 Elsevier Inc. All rights reserved.
引用
收藏
页码:1758 / 1762
页数:5
相关论文
共 50 条
  • [31] Towards optimal scheduling policy for heterogeneous memory architecture in many-core system
    Geunchul Park
    Seungwoo Rho
    Jik-Soo Kim
    Dukyun Nam
    Cluster Computing, 2019, 22 : 121 - 133
  • [32] Design and verification of a lightweight reliable virtual machine monitor for a many-core architecture
    Yuehua Dai
    Yi Shi
    Yong Qi
    Jianbao Ren
    Peijian Wang
    Frontiers of Computer Science, 2013, 7 : 34 - 43
  • [33] Godson-T: An Efficient Many-Core Architecture for Parallel Program Executions
    Fan, Dong-Rui
    Yuan, Nan
    Zhang, Jun-Chao
    Zhou, Yong-Bin
    Lin, Wei
    Song, Feng-Long
    Ye, Xiao-Chun
    Huang, He
    Yu, Lei
    Long, Guo-Ping
    Zhang, Hao
    Liu, Lei
    JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY, 2009, 24 (06) : 1061 - 1073
  • [34] Godson-T:An Efficient Many-Core Architecture for Parallel Program Executions
    范东睿
    袁楠
    张军超
    周永彬
    林伟
    宋风龙
    叶笑春
    黄河
    余磊
    龙国平
    张浩
    刘磊
    JournalofComputerScience&Technology, 2009, 24 (06) : 1061 - 1073
  • [35] Parallelizing and optimizing a bioinformatics pairwise sequence alignment algorithm for many-core architecture
    Diaz, David
    Jose Esteban, Francisco
    Hernandez, Pilar
    Antonio Caballero, Juan
    Dorado, Gabriel
    Galvez, Sergio
    PARALLEL COMPUTING, 2011, 37 (4-5) : 244 - 259
  • [36] Design and verification of a lightweight reliable virtual machine monitor for a many-core architecture
    Dai, Yuehua
    Shi, Yi
    Qi, Yong
    Ren, Jianbao
    Wang, Peijian
    FRONTIERS OF COMPUTER SCIENCE, 2013, 7 (01) : 34 - 43
  • [37] An on-node scalable sparse incomplete LU factorization for a many-core iterative solver with Javelin
    Booth, Joshua Dennis
    Bolet, Gregory
    PARALLEL COMPUTING, 2020, 94-95 (94-95)
  • [38] DRACON: A Dedicated Hardware Infrastructure for Scalable Run-Time Management on Many-Core Systems
    Gregorek, Daniel
    Rust, Jochen
    Garcia-Ortiz, Alberto
    IEEE ACCESS, 2019, 7 : 121931 - 121948
  • [39] MCMalloc: A Scalable Memory Allocator for Multithreaded Applications on a Many-Core Shared-Memory Machine
    Umayabara, Akira
    Yamana, Hayato
    2017 IEEE INTERNATIONAL CONFERENCE ON BIG DATA (BIG DATA), 2017, : 4846 - 4848
  • [40] Large-Scale Molecular Dynamics Simulation Based on Heterogeneous Many-Core Architecture
    Zhou, Xu
    Wei, Zhiqiang
    Lu, Hao
    He, Jiaqi
    Gao, Yuan
    Hu, Xiaotong
    Wang, Cunji
    Dong, Yujie
    Liu, Hao
    JOURNAL OF CHEMICAL INFORMATION AND MODELING, 2024, 64 (03) : 851 - 861