Rapid IP design of variable-length Cached-FFT processor for OFDM-based communication systems

Fast Fourier Transform (FFT) and Inverse FFT (IFFT) are adopted as the demodulation/modulation kernels in OFDM systems. The lengths of FFT/IFFT operations may vary in different applications of OFDM systems. Moreover, due to the trend of system-on-chip (SOC), rapid prototyping and intelligent soft IP designs are important design methodologies. In this paper, we design and implement a variable-length FFT processor to cover different applications of OFDM systems. We propose an efficient design flow which makes re-designing an FFT processor rapid and easy. We adopt cached-memory structure in the FFT processor for low-power consumption issue. Besides, we employ block-floating-point (BFP) arithmetic to acquire high signal to quantization noise ratio (SQNR). Finally, we implement this processor with TSMCO.18 mu m 1P6M CMOS technology. The simulation results show that the chip can perform 64 similar to 2048-point FFT operations at 75 MHz which meet the speed requirements of most OFDM standards such as WLAN, ADSL, VDSL (256 similar to 2048), DAB, and DVB (2k mode).