Comparison of the performance improvement for the two novel SOI-tunnel FETs with the lateral dual-gate and triple-gate

In this paper, we present two silicon-on-insulator tunnel field-effect transistors (SOI-TFETs), referred as a lateral dual-gate TFET and a lateral triple-gate TFET, which consist of one or two vertical thin vertical dielectric layers within the original front-gate region and form the separate dual-gate or triple-gate structure. Using calibrated two-dimensional Synopsys Sentaurus TCAD simulation, we demonstrate that the proposed novel TFETs have relatively higher I-on and significantly lower I-off due to the modulating effect of the multiple gate voltages on the channel barrier. We also compare and analyze improvements in I-on/I-off for the two novel SOI-TFETs and a conventional SOI-TFET. The proposed new TFETs exhibit a high I-on/I-off ratio of 10(4) ~ 10(8) for a channel length of 22 nm. Our results reveal that the performance of the lateral triple-gate TFET is superior to that of the dual-gate TFET, yielding higher on-state current and lower off-state current.