A digital vision chip specialized for high-speed target tracking

被引:103
作者
Komuro, T [1 ]
Ishii, I
Ishikawa, M
Yoshida, A
机构
[1] Univ Tokyo, Grad Sch Informat Sci & Technol, Tokyo 1138656, Japan
[2] Tokyo Univ Agr & Technol, Dept Elect & Elect Engn, Tokyo 1848588, Japan
[3] Nippon Precis Circuits Inc, Prod Dev Dept, Tokyo 1358430, Japan
关键词
target tracking; vision chip;
D O I
10.1109/TED.2002.807255
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper describes a new vision chip architecture for high-speed target tracking. The processing speed and the number of pixels are improved by hardware implementation of a special algorithm which utilizes a property of high-speed vision and introduction of bit-serial and cumulative summation circuits. As a result, 18 objects in a 128 x 128 image can be tracked in 1 ms. Based on the architecture, a prototype chip has been developed; 64 x 64 pixels are integrated in 7 nun square chip and the power consumption for obtaining the centroid of an object per every 1 ms is 112 mW. Some experiments are performed on the evaluation board which is developed for evaluation under the condition of actual operation. High-speed target tracking including multitarget tracking with collision and separation has successfully been achieved.
引用
收藏
页码:191 / 199
页数:9
相关论文
共 14 条
  • [1] A PROGRAMMABLE ARTIFICIAL RETINA
    BERNARD, TM
    ZAVIDOVIQUE, BY
    DEVOS, FJ
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1993, 28 (07) : 789 - 798
  • [2] Computational sensor for visual tracking with attention
    Brajovic, V
    Kanade, T
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1998, 33 (08) : 1199 - 1207
  • [3] VLSI implementation of a focal plane image processor - A realization of the near-sensor image processing concept
    Eklund, JE
    Svensson, C
    Astrom, A
    [J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 1996, 4 (03) : 322 - 335
  • [4] A foveated silicon retina for two-dimensional tracking
    Etienne-Cummings, R
    Van der Spiegel, J
    Mueller, P
    Zhang, MZ
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 2000, 47 (06): : 504 - 517
  • [5] Ishii I, 1996, IEEE INT CONF ROBOT, P2309, DOI 10.1109/ROBOT.1996.506508
  • [6] Ishikawa M, 2001, 2001 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, P1, DOI 10.1109/VLSIC.2001.934175
  • [7] Ishikawa M., 1992, P IEEE RSJ INT C INT, P373
  • [8] High speed target tracking vision chip
    Komuro, T
    Ishii, I
    Ishikawa, M
    Yoshida, A
    [J]. 5TH INTERNATIONAL WORKSHOP ON COMPUTER ARCHITECTURES FOR MACHINE PERCEPTION, PROCEEDINGS, 2000, : 49 - 56
  • [9] Vision chip architecture using general-purpose processing elements for 1ms vision system
    Komuro, T
    Ishii, I
    Ishikawa, M
    [J]. CAMP'97 - FOURTH IEEE INTERNATIONAL WORKSHOP ON COMPUTER ARCHITECTURE FOR MACHINE PERCEPTION, PROCEEDINGS, 1997, : 276 - 279
  • [10] A SILICON MODEL OF EARLY VISUAL PROCESSING
    MEAD, CA
    MAHOWALD, MA
    [J]. NEURAL NETWORKS, 1988, 1 (01) : 91 - 97