A strained N-channel impact-ionization MOS (I-MOS) transistor with elevated silicon-carbon source/drain for performance enhancement

被引：0

作者：

Toh, Eng-Huat ^{[1
]}

Wang, Grace Huiqi ^{[1
]}

Lo, Guo-Qiang ^{[2
]}

Choy, Siew-Fong ^{[1
,2
]}

Chan, Lap

Samudra, Ganesh ^{[1
]}

Yeo, Yee-Chia ^{[1
]}

机构：

[1] NUS, Dept Elect & Comp Engn, Silicon Nanodevice Lab, Singapore 117576, Singapore

[2] Inst Microelect, Singapore 117685, Singapore

来源：

2007 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATIONS (VLSI-TSA), PROCEEDINGS OF TECHNICAL PAPERS | 2007年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper reports the first demonstration of strain engineering in Impact-ionization MOS (I-MOS) transistors for performance enhancement. An epitaxial silicon-carbon (Si0.99C0.01) source/drain was integrated in a CMOS-compatible I-MOS fabrication process. The lattice mismatch between Si0.99C0.01 and Si was exploited for the realization of strained I-MOS devices. Uniaxial tensile strain in the channel and impact-ionization regions contributes to enhanced electron transport and device characteristics. The strained I-MOS technology demonstrates an excellent subthreshold swing of 5.3 mV/decade at room temperature for devices with 100 nm gate length. Compared to control I-MOS devices with Si raised source/drain, strained I-MOS devices show significantly higher drive currents and a steeper subthreshold swing.

引用

页码：86 / +

页数：2