A Novel High Latch-Up Immunity Electrostatic Discharge Protection Device for Power Rail in High-Voltage ICs

被引:4
作者
Zhang, Chunwei [1 ]
Liu, Siyang [1 ]
Xu, Kaikai [2 ]
Wei, Jiaxing [1 ]
Ye, Ran [1 ]
Sun, Weifeng [1 ]
Su, Wei [3 ]
Zhang, Aijun [3 ]
Ma, Shulang [3 ]
Lin, Feng [3 ]
Sun, Guipeng [3 ]
机构
[1] Southeast Univ, Natl Engn Res Ctr ASIC, Nanjing 210096, Jiangsu, Peoples R China
[2] Univ Elect Sci & Technol China, State Key Lab Elect Thin Films & Integrated Devic, Chengdu 610054, Peoples R China
[3] CSMC Technol Corp, Wuxi 214000, Peoples R China
基金
中国博士后科学基金;
关键词
Electrostatic discharge; high voltage; holding voltage; latch-up immunity; power rail;
D O I
10.1109/TDMR.2016.2544350
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this letter, a novel high latch-up immunity electrostatic discharge protection device that can be equivalent to a PNP-type bipolar junction transistor (BJT) and a series-connected Zener diode is proposed. For the proposed device, the emitter of its BJT is formed by Zener implantation instead of conventional P-plus. In this way, the high latch-up immunity can be achieved by the Zener implantation dose and window designing. Meanwhile, the proposed device exhibits excellent voltage clamp capability and 2.2 times large second breakdown current as a generally used diode.
引用
收藏
页码:266 / 268
页数:3
相关论文
共 10 条
[1]   Combined MOS-IGBT-SCR Structure for a Compact High-Robustness ESD Power Clamp in Smart Power SOI Technology [J].
Arbess, Houssam ;
Bafleur, Marise ;
Tremouilles, David ;
Zerarka, Moustafa .
IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2014, 14 (01) :432-440
[2]   Investigation of high voltage SCR-LDMOS ESD device for 150 V SOI BCD process [J].
Cai Xiaowu ;
Wei Junxiu ;
Liang Chao ;
Gao Zhe ;
Lv Chuan .
MICROELECTRONICS RELIABILITY, 2013, 53 (06) :861-866
[3]   A Method to Prevent Strong Snapback in LDNMOS for ESD Protection [J].
Fan, Hang ;
Jiang, Lingli ;
Zhang, Bo .
IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2013, 13 (01) :50-53
[4]   Analytical description of the injection ratio of self-biased bipolar transistors under the very high injection conditions of ESD events [J].
Gendron, A. ;
Renaud, P. ;
Bafleur, M. ;
Nolhier, N. .
SOLID-STATE ELECTRONICS, 2008, 52 (05) :663-674
[5]  
GENDRON A, 2006, P EOS ESD S SEP, P69
[6]   An SCR-Incorporated BJT Device for Robust ESD Protection With High Latchup Immunity in High-Voltage Technology [J].
Huang, Chih-Yao ;
Chiu, Fu-Chien ;
Chen, Quo-Ker ;
Lai, Ming-Fang ;
Tseng, Jen-Chou .
IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2012, 12 (01) :113-123
[7]   ESD protection solutions for high voltage technologies [J].
Keppens, B ;
Mergens, MPJ ;
Trinh, CS ;
Russ, CC ;
Van Camp, B ;
Verhaege, KG .
MICROELECTRONICS RELIABILITY, 2006, 46 (5-6) :677-688
[8]   Double snapback characte'ristics in high-voltage nMOSFETs and the impact to on-chip ESD protection design [J].
Ker, MD ;
Lin, KH .
IEEE ELECTRON DEVICE LETTERS, 2004, 25 (09) :640-642
[9]   Electrical Characteristics and Thermal Reliability of Stacked-SCRs ESD Protection Device for High Voltage Applications [J].
Koo, Yong Seo ;
Kim, Dong Su ;
Eo, Jin Woo .
JOURNAL OF POWER ELECTRONICS, 2012, 12 (06) :947-953
[10]   Layout Consideration and Circuit Solution to Prevent EOS Failure Induced by Latchup Test in a High-Voltage Integrated Circuits [J].
Tsai, Hui-Wen ;
Ker, Ming-Dou .
IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2014, 14 (01) :493-498