Clock Repeater Characterization for Jitter-Aware Clock Tree Synthesis

被引：0

作者：

Figueiredo, Monica ^{[1
]}

Aguiar, Rui L. ^{[2
]}

机构：

[1] Escola Super Tecnol & Gestao, Inst Politecn Leiria, Aveiro, Portugal

[2] Univ Aveiro, Inst Telecomun, Dpt Elect & Telecomun, Aveiro, Portugal

来源：

INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION | 2010年 / 5953卷

关键词：

Jitter Model; Clock Repeaters; CTS; DISTRIBUTION NETWORKS; NOISE; POWER;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a simple jitter model for clock repeaters. The model is scalable and technology independent; which makes it suitable for integration in current clock tree synthesis algorithms. It is based on the timing characterization of a reference inverter, which can be performed for different process corners to account for process variability. Simulation results show that the model is accurate to within 10% for the most common inverter and NAND based repeaters.

引用

页码：46 / +

页数：2

共 14 条

[1] Digital ground bounce reduction by supply current shaping and clock frequency modulation
Badaroglu, M
Wambacq, P
Van der Plas, G
Donnay, S
Gielen, GGE
De Man, HJ
[J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2005, 24 (01) : 65 - 76
[2] Dynamic thermal clock skew compensation using tunable delay buffers
Chakraborty, Ashutosh
Duraisami, Karthik
Sathanur, Ashoka
Sithambaram, Prassanna
Benini, Luca
Macii, Alberto
Macii, Enrico
Poncino, Massimo
[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2008, 16 (06) : 639 - 649
[3] Buffer delay change in the presence of power and ground noise
Chen, LH
Marek-Sadowska, M
Brewer, F
[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2003, 11 (03) : 461 - 473
[4] Clock distribution networks in synchronous digital integrated circuits
Friedman, EG
[J]. PROCEEDINGS OF THE IEEE, 2001, 89 (05) : 665 - 692
[5] Jitter and phase noise in ring oscillators
Hajimiri, A
Limotyrakis, S
Lee, TH
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1999, 34 (06) : 790 - 804
[6] Statistical analysis of clock skew variation in H-tree structure
Hashimoto, M
Yamamoto, T
Onodera, H
[J]. 6TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS, 2005, : 402 - 407
[7] Jang J H, 2008, 12 IEEE WORKSH SIGN, P1
[8] Single edge clock (SEC) distribution for improved latency, skew, and jitter performance
Mueller, Jeff
Saleh, Resve
[J]. 21ST INTERNATIONAL CONFERENCE ON VLSI DESIGN: HELD JOINTLY WITH THE 7TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, PROCEEDINGS, 2008, : 214 - 219
[9] OBRIEN PR, 1989, INT C COMP AID DES, P512, DOI DOI 10.1109/ICCAD.1989.77002
[10] OSORIO JF, 2005, 20 C DES CIRC INT SY, P1

← 1 2 →