Before manufacturing, each chip design must be inspected for possible errors: For example, design rule checking is used to check, for adherence to the physical manufacturing rules, and static timing analysis is used to verify that the design has adequate performance. Although modern chip designs are invariably specified hierarchically, verification algorithms can treat this hierarchy in different ways. The most straight forward in a W way to verify a hierarchical design is to expand (or flatten) the hierarchy, then do the test. Since most verification, algorithms involve at least sorting the data, such algorithms are at least O(N log N), where N is the size of the, flattened hierarchy. Alternatively, a verification tool can try to use the hierarchy rather than flattening it. One form of hierarchical verification involves verifying each cell, generating a model (also called an abstract) for each cell, and then checking all interactions between cells by using their abstracts. Under some conditions, this may. be more efficient than flattening the hierarchy and then verifying. In particular, if the size, of the abstract is 0(n(a)) for a cell containing n primitives, and. the time to verify a cell and generate the abstract is 0(n(b)), then the complete verification of all levels of the hierarchy is 0 (N), provided ab < 1.
