A new modeling technique for mixed-mode simulation of CMOS circuits

An efficient and accurate simulation of digital circuits is of utmost importance in VLSI design to correctly predict timing performance and to accurately predict electrical waveform at all the nodes which link to analog blocks. To achieve this objective, an improved technique to correctly model the conductance of RIGS device for electrical logic simulation (ELogic) of CMOS circuits is proposed [7]. The technique is general and applicable to any integrable analytic device current model. The model is implemented in a well-known mixed-mode simulator iSPLICE3. The examples show that the improved technique is able to correctly predict several complete electrical waveforms with a large voltage step of 1 V with only five logic levels to yield al least an order of magnitude computational time advantage over the circuit simulation with virtually minimal loss in the accuracy.