Correlation between barrier integrity and TDDB performance of copper porous low-k interconnects

被引：13
作者：
Tökei, Z
Patz, M
Schmidt, M
Iacopi, F
Demuynck, S
Maex, K
机构：
[1] IMEC, B-3001 Heverlee, Belgium
[2] JSR Corp, IMEC, Ibaraki 3050841, Japan
[3] Infineon Technol AG, IMEC, D-81541 Munich, Germany
[4] Katholieke Univ Leuven, Elect Engn Dept, Louvain, Belgium
来源：
MICROELECTRONIC ENGINEERING | 2004年 / 76卷 / 1-4期
关键词：
barrier deposition; barrier integrity; iPVD; TDDB reliability; porous low-k; porous MSQ; p-MSQ;
D O I：
10.1016/j.mee.2004.07.057
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Time Dependent Dielectric Breakdown performance of a fully dense and a porous metal diffusion barrier was evaluated on a porous methyl-silsesquioxane low-k material. By changing the barrier deposition process, the barrier integrity on damascene sidewalls can be improved and sealing of the low-k sidewalls is achieved with a barrier thickness value of about 8 nm. A clear correlation between barrier integrity and interconnect reliability was evidenced and an improved barrier integrity leads to increased lifetimes. (C) 2004 Elsevier B.V. All rights reserved.
引用
收藏
页码：70 / 75
页数：6
相关论文
共 18 条
  • [1] Post patterning meso porosity creation: A potential solution for pore sealing
    Caluwaerts, R
    Van Hove, M
    Beyer, G
    Hoofman, RJOM
    Struyf, H
    Verheyden, GJAM
    Waeterloos, J
    Tokei, Z
    Iacopi, F
    Carbonell, L
    Le, QT
    Das, A
    Vos, I
    Demuynck, S
    Maex, K
    [J]. PROCEEDINGS OF THE IEEE 2003 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2003, : 242 - 244
  • [2] CALVERT JM, 2003, SEMICOND INT, V26, P56
  • [3] DONOHUE H, 2002, P ADV MET C AMC, P575
  • [4] Impact of LKD5109™ low-k to cap/liner interfaces in single damascene process and performance
    Iacopi, F
    Patz, M
    Vos, I
    Tokei, Z
    Sijmus, B
    Le, QT
    Sleeckx, E
    Eyckens, B
    Struyf, H
    Das, A
    Maex, K
    [J]. MICROELECTRONIC ENGINEERING, 2003, 70 (2-4) : 293 - 301
  • [5] Diffusion barrier integrity and electrical performance of Cu/porous dielectric damascene lines
    Iacopi, F
    Tokei, Z
    Stucchi, M
    Lanckmans, F
    Maex, K
    [J]. IEEE ELECTRON DEVICE LETTERS, 2003, 24 (03) : 147 - 149
  • [6] Factors affecting an efficient sealing of porous low-k dielectrics by physical vapor deposition Ta(N) thin films
    Iacopi, F
    Tokei, Z
    Le, QT
    Shamiryan, D
    Conard, T
    Brijs, B
    Kreissig, U
    Van Hove, M
    Maex, K
    [J]. JOURNAL OF APPLIED PHYSICS, 2002, 92 (03) : 1548 - 1554
  • [7] Reliability improvement of Cu/low-k dual damascene interconnects using the depo/etch barrier process by newly developed I-PVD
    Motoyama, K
    Faguet, J
    Katsuki, J
    Chung, G
    Tonegawa, T
    Miyamoto, H
    [J]. PROCEEDINGS OF THE IEEE 2002 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2002, : 268 - 270
  • [8] Porous low k pore sealing process study for 65-nm and below technologies
    Mourier, T
    Jousseaume, V
    Fusalba, F
    Lecornec, C
    Maury, P
    Passemard, G
    Haumesser, PH
    Maîtrejean, S
    Cordeau, M
    Pantel, R
    Pierre, F
    Fayolle, M
    Feldis, H
    [J]. PROCEEDINGS OF THE IEEE 2003 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2003, : 245 - 247
  • [9] Leakage, breakdown, and TDDB characteristics of porous low-k silica-based interconnect dielectrics
    Ogawa, ET
    Kim, J
    Haase, GS
    Mogul, HC
    McPherson, JW
    [J]. 41ST ANNUAL PROCEEDINGS: INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, 2003, : 166 - 172
  • [10] Advanced i-PVD barrier metal deposition technology for 90nm Cu interconnects
    Park, KC
    Kim, IR
    Suh, BS
    Choi, SM
    Song, WS
    Wee, YJ
    Lee, SG
    Chung, JS
    Chung, JH
    Hah, SR
    Ahn, JH
    Lee, KJ
    Kang, HK
    Suh, KP
    [J]. PROCEEDINGS OF THE IEEE 2003 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2003, : 165 - 167
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