An ECG Recording Front-End With Continuous-Time Level-Crossing Sampling

被引：46

作者：

Li, Yongjia ^{[1
]}

Mansano, Andre L. ^{[1
]}

Yuan, Yuan ^{[2
]}

Zhao, Duan ^{[1
]}

Serdijn, Wouter A. ^{[1
]}

机构：

[1] Delft Univ Technol, Sect Bioelect, NL-2628 CD Delft, Netherlands

[2] MStar Semicond Inc, Shanghai 201203, Peoples R China

来源：

IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS | 2014年 / 8卷 / 05期

关键词：

Analog-to-digital conversion; asynchronous ADC; biomedical recording system; ECG recording; level-crossing ADC; level-crossing sampling; offset calibration; pseudo-resistor; voltage-to-current converter; INSTRUMENTATION AMPLIFIER; DELAY ELEMENT; CMOS; ADC;

D O I：

10.1109/TBCAS.2014.2359183

中图分类号：

R318 [生物医学工程];

学科分类号：

0831 ;

摘要：

An ECG recording front-end with a continuoustime asynchronous level-crossing analog-to-digital converter (LC-ADC) is proposed. The system is a voltage and current mixed-mode system, which comprises a low noise amplifier (LNA), a programmable voltage-to-current converter (PVCC) as a programmable gain amplifier (PGA) and an LC-ADC with calibration DACs and an RC oscillator. The LNA shows an input referred noise of 3.77 mu Vrms over 0.06 Hz-950 Hz bandwidth. The total harmonic distortion (THD) of the LNA is 0.15% for a 10 mV(pp) input. The ECG front-end consumes 8.49 mu W from a 1 V supply and achieves an ENOB up to 8 bits. The core area of the proposed front-end is 690 x 710 mu m2, fabricated in a 0.18 mu m CMOS technology.

引用

页码：626 / 635

页数：10

共 30 条

[1] Input-Feature Correlated Asynchronous Analog to Information Converter for ECG Monitoring [J].

Agarwal, Ritika ;

Sonkusale, Sameer R. .

IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, 2011, 5 (05) :459-467

[2] New class of asynchronous A/D converters based on time quantization [J].

Allier, E ;

Sicard, G ;

Fesquet, L ;

Renaudin, M .

NINTH INTERNATIONAL SYMPOSIUM ON ASYNCHRONOUS CIRCUITS AND SYSTEMS, PROCEEDINGS, 2003, :196-205

[3] Compressed sensing [J].

Donoho, DL .

IEEE TRANSACTIONS ON INFORMATION THEORY, 2006, 52 (04) :1289-1306

[4] A 1.8 μW 60 nV/√Hz Capacitively-Coupled Chopper Instrumentation Amplifier in 65 nm CMOS for Wireless Sensor Nodes [J].

Fan, Qinwen ;

Sebastiano, Fabio ;

Huijsing, Johan H. ;

Makinwa, Kofi A. A. .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2011, 46 (07) :1534-1543

[5]

Foster J., 1991, P IEEE SOUTHEASTCON, V2, P861

[6] A 0.45 V 100-Channel Neural-Recording IC With Sub-μW/Channel Consumption in 0.18 μm CMOS [J].

Han, Dong ;

Zheng, Yuanjin ;

Rajkumar, Ramamoorthy ;

Dawe, Gavin Stewart ;

Je, Minkyu .

IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, 2013, 7 (06) :735-746

[7] The design of integrated circuits to observe brain activity [J].

Harrison, Reid R. .

PROCEEDINGS OF THE IEEE, 2008, 96 (07) :1203-1216

[8] A low-power low-noise CMOS amplifier for neural recording applications [J].

Harrison, RR ;

Charles, C .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2003, 38 (06) :958-965

[9] A LOW-NOISE AMPLIFIER FOR SWITCHED CAPACITOR FILTERS [J].

JOLLY, RD ;

MCCHARLES, RH .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1982, 17 (06) :1192-1194

[10] A low-voltage, low-power CMOS delay element [J].

Kim, G ;

Kim, MK ;

Chang, BS ;

Kim, W .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1996, 31 (07) :966-971

← 1 2 3 →