Reuse of models and testbenches at different levels of abstraction

When VHDL is used to support top-down design, a collection of VHDL models is produced at multiple levels of abstraction. Efficient use of these models during the design process requires proper organization of these models into VHDL libraries to maximize reuse and localize changes. Reuse is also supported by VHDL configuration bodies for the testbenches which make it easy to reconfigure the models for the series of tests required. This paper discusses the organization of such a collection of models into VHDL libraries, the use of configuration bodies to configure models, and issues relating to the integration of mixed level of abstraction models.