High-performance Architecture of H.264 Integer-pixel Motion Estimation IP for Real-time 1080HD Video CODEC

被引：0

作者：

Chang, Hoyoung ^{[1
]}

Kim, Soojin ^{[1
]}

Lee, Seonyoung ^{[1
]}

Cho, Kyeongsoon ^{[1
]}

机构：

[1] Hankuk Univ Foreign Studies, Dept Elect & Informat Engn, Yongin, Gyeonggi, South Korea

来源：

IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS | 2009年

关键词：

VLSI ARCHITECTURE;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We propose a new H.264 integer-pixel motion estimation algorithm and circuit architecture to improve the processing speed. The proposed circuit supports 7 kinds of variable block sizes and generates 41 motion vectors. The implemented IP based on the proposed algorithm and architecture processes 60 image frames per second for 1080HD video at the operating frequency of 45.5MHz.

引用

页码：419 / 422

页数：4

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