Compiler-Directed Power Management for Superscalars

被引：3

作者：

Haj-Yihia, Jawad ^{[1
]}

Ben Asher, Yosi ^{[2
]}

Rotem, Efraim ^{[1
]}

Yasin, Ahmad ^{[1
]}

Ginosar, Ran ^{[3
]}

机构：

[1] Intel Corp, Santa Clara, CA 95051 USA

[2] Univ Haifa, IL-31999 Haifa, Israel

[3] Technion Israel Inst Technol, IL-32000 Haifa, Israel

来源：

ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION | 2014年 / 11卷 / 04期

关键词：

Performance; Design; Algorithms; Compiler assisted; power management; energy; power modeling; VOLTAGE;

D O I：

10.1145/2685393

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Modern superscalar CPUs contain large complex structures and diverse execution units, consuming wide dynamic power range. Building a power delivery network for the worst-case power consumption is not energy efficient and often is impossible to fit in small systems. Instantaneous power excursions can cause voltage droops. Power management algorithms are too slow to respond to instantaneous events. In this article, we propose a novel compiler-directed framework to address this problem. The framework is validated on a 4th Generation Intel (R) Core (TM) processor and with simulator on output trace. Up to 16% performance speedup is measured over baseline for the SPEC CPU2006 benchmarks.

引用

页数：21

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