Fast-switching frequency synthesizer with a discriminator-aided phase detector

被引：66

作者：

Yang, CY ^{[1
]}

Liu, SI ^{[1
]}

机构：

[1] Natl Taiwan Univ, Dept Elect Engn, Taipei 10617, Taiwan

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2000年 / 35卷 / 10期

关键词：

bandwidth adjusting; fast acquisition; fast locking; frequency synthesizers; phase detectors; phase-locked loops;

D O I：

10.1109/4.871321

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A phase-locked loop (PLL) with a fast-locked discriminator-aided phase detector (DAPD) is presented. Compared with the conventional phase detector (PD), the proposed fast-locked PD reduces the PLL pull-in time and enhances the switching speed, while maintaining better noise bandwidth. The synthesizer has been implemented in a 0.35-mu m CMOS process, and the output phase noise is -99 dBc/Hz at 100-kHz offset. Under the supply voltage of 3.3 V, its power consumption is 120 mW.

引用

页码：1445 / 1452

页数：8

共 18 条

[1] [Anonymous], 1984, PHASE LOCKED LOOPS T
[2] A 1.2 GHz CMOS dual-modulus prescaler using new dynamic D-type flip-flops
Chang, BS
Park, JB
Kim, WC
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1996, 31 (05) : 749 - 752
[3] Gardner F. M., 1979, PHASELOCK TECHNIQUES
[4] CHARGE-PUMP PHASE-LOCK LOOPS
GARDNER, FM
[J]. IEEE TRANSACTIONS ON COMMUNICATIONS, 1980, 28 (11) : 1849 - 1858
[5] Speed optimization of edge-triggered CMOS circuits for Gigahertz single-phase clocks
Huang, QT
Rogenmoser, R
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1996, 31 (03) : 456 - 465
[6] High speed differential voltage clamped current mode ring oscillator
Jeong, DY
Chae, SH
Song, WC
Cho, GH
[J]. ELECTRONICS LETTERS, 1997, 33 (13) : 1102 - 1103
[7] Keese WO., 1995, FAST LOCKING SCHEME
[8] A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL
Kim, S
Lee, K
Moon, Y
Jeong, DK
Choi, YH
Lim, HK
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1997, 32 (05) : 691 - 700
[9] REDUCED PULL-IN TIME OF PHASE-LOCKED LOOPS USING A SIMPLE NONLINEAR PHASE-DETECTOR
LARSSON, P
[J]. IEE PROCEEDINGS-COMMUNICATIONS, 1995, 142 (04): : 221 - 226
[10] High-speed architecture for a programmable frequency divider and a dual-modulus prescaler
Larsson, PO
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1996, 31 (05) : 744 - 748

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