Fast-switching frequency synthesizer with a discriminator-aided phase detector

被引：66

作者：

Yang, CY ^{[1
]}

Liu, SI ^{[1
]}

机构：

[1] Natl Taiwan Univ, Dept Elect Engn, Taipei 10617, Taiwan

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2000年 / 35卷 / 10期

关键词：

bandwidth adjusting; fast acquisition; fast locking; frequency synthesizers; phase detectors; phase-locked loops;

D O I：

10.1109/4.871321

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A phase-locked loop (PLL) with a fast-locked discriminator-aided phase detector (DAPD) is presented. Compared with the conventional phase detector (PD), the proposed fast-locked PD reduces the PLL pull-in time and enhances the switching speed, while maintaining better noise bandwidth. The synthesizer has been implemented in a 0.35-mu m CMOS process, and the output phase noise is -99 dBc/Hz at 100-kHz offset. Under the supply voltage of 3.3 V, its power consumption is 120 mW.

引用

页码：1445 / 1452

页数：8

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