Analysis of a Novel Metal Implant Junctionless Tunnel FET for Better DC and Analog/RF Electrostatic Parameters

被引:63
作者
Tirkey, Sukeshni [1 ]
Sharma, Dheeraj [1 ]
Yadav, Dharmendra Singh [1 ]
Yadav, Shivendra [1 ]
机构
[1] Pandit Dwarka Prasad Mishra Indian Inst Informat, Elect & Commun Discipline, Jabalpur 482005, India
关键词
Abruptness; ambipolar nature; metal implant junctionless tunnel FET ( JL-TFET); steep subthreshold slope; FIELD-EFFECT TRANSISTOR; ATOMIC LAYER DEPOSITION; DEVICE RELIABILITY; WORK FUNCTION; GATE; PERFORMANCE; DESIGN; DRAIN;
D O I
10.1109/TED.2017.2730922
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Steep rise in the subthreshold slope, high current driving capability, and negligible ambipolarity are the major prerequisite conditions of tunnel FETs (TFETs) to make it applicable for Analog/RF circuit applications. Along with that, fabrication of physically doped TFETs is a major concern in device technology. In this context, this paper deals with junctionless TFET with a metal implanted in the oxide at the source/channel and drain/channel junctions to enhance its ON-current and reduce the ambipolar nature. The metal introduced at the source/channel junction generates abruptness and brings improvement in subthreshold slope, which increases the current driving capability of the device. Similarly, the metal implanted at the drain/channel junction widens the energy gap at the same junction to reduce the ambipolar behavior of the device. This also contributes to the enhancement of dc and analog/RF performance of the device. The selection of appropriate work function and length of the metal implanted at both the interfaces is important to maintain the improved ON-current and ambipolarity. This optimization gives idea of keeping the appropriate length, which provides direction toward practical feasibility at the experimental level.
引用
收藏
页码:3943 / 3950
页数:8
相关论文
共 32 条
[1]   Controlling Ambipolar Current in Tunneling FETs Using Overlapping Gate-on-Drain [J].
Abdi, Dawit B. ;
Kumar, M. Jagadesh .
IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 2014, 2 (06) :187-190
[2]  
[Anonymous], 2014, ATLAS DEV SIM SOFTW
[3]   A high performance gate engineered charge plasma based tunnel field effect transistor [J].
Bashir, Faisal ;
Loan, Sajad A. ;
Rafat, M. ;
Alamoud, Abdul Rehman M. ;
Abbasi, Shuja A. .
JOURNAL OF COMPUTATIONAL ELECTRONICS, 2015, 14 (02) :477-485
[4]   Double-gate tunnel FET with high-κ gate dielectric [J].
Boucart, Kathy ;
Mihai Ionescu, Adrian .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2007, 54 (07) :1725-1733
[5]   Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec [J].
Choi, Woo Young ;
Park, Byung-Gook ;
Lee, Jong Duk ;
Liu, Tsu-Jae King .
IEEE ELECTRON DEVICE LETTERS, 2007, 28 (08) :743-745
[6]   Hetero-Gate-Dielectric Tunneling Field-Effect Transistors [J].
Choi, Woo Young ;
Lee, Woojun .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2010, 57 (09) :2317-2319
[7]   Device scaling limits of Si MOSFETs and their application dependencies [J].
Frank, DJ ;
Dennard, RH ;
Nowak, E ;
Solomon, PM ;
Taur, Y ;
Wong, HSP .
PROCEEDINGS OF THE IEEE, 2001, 89 (03) :259-288
[8]   Atomic Layer Deposition: An Overview [J].
George, Steven M. .
CHEMICAL REVIEWS, 2010, 110 (01) :111-131
[9]   Junctionless Tunnel Field Effect Transistor [J].
Ghosh, Bahniman ;
Akram, Mohammad Waseem .
IEEE ELECTRON DEVICE LETTERS, 2013, 34 (05) :584-586
[10]   Analog performance of Si junctionless tunnel field effect transistor and its improvisation using III-V semiconductor [J].
Goswami, Yogesh ;
Ghosh, Bahniman ;
Asthana, Pranav Kumar .
RSC ADVANCES, 2014, 4 (21) :10761-10765