Incorporating Quantum Effects in Ultralow Power (ULP) Subthreshold Logic Design With Junctionless Nanowire Transistor

被引：3
作者：
Rai, Nivedita [1 ]
Ahuja, Khushboo [1 ]
Semwal, Sandeep [1 ]
Kranti, Abhinav [1 ]
机构：
[1] Indian Inst Technol Indore, Dept Elect Engn, Low Power Nanoelect Res Grp, Indore 453552, Madhya Pradesh, India
来源：
IEEE TRANSACTIONS ON ELECTRON DEVICES | 2022年 / 69卷 / 07期
关键词：
Logic gates; Electric potential; Doping; Transistors; Semiconductor process modeling; Silicon; Logic design; Cylindrical; circuit; junctionless; logic; model; nanowire; quantum; subthreshold; transistor; THRESHOLD VOLTAGE; COMPACT MODEL; GATE; MOSFETS;
D O I：
10.1109/TED.2022.3172045
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This article proposes a ultralow-power (ULP) subthreshold model for short-channel nanowire underlap junctionless transistor (JLT-U) incorporating quantum confinement effect. Considering JLT-U as a confined quantum harmonic oscillator, consistent values of subband energies are obtained for wide ranges of nanowire diameter and channel doping. The subband energy, electron line density, drain current, and threshold voltage of JLT-U are determined and validated with TCAD simulations. DC figures of merit (voltage swing, switching threshold, voltage gain, and noise margin) of ULP subthreshold inverter are investigated using a simplified circuit model. The approach presented in this article is of utmost benefit for device/circuit designers aiming for ULP subthreshold logic technology.
引用
收藏
页码：3983 / 3989
页数：7
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