3D On-Chip Memory for the Vector Architecture

Vector supercomputers play an important roll in a high performance computing area because vector systems can achieve a high computational efficiency for large scale scientific applications. The most important factor of a vector supercomputer is its high memory bandwidth between the processor and the off-chip main memory. However, it is inevitable to decrease the ratio of memory bandwidth to floating-point operation rate due to several hardware limitations, which prevent future vector processors from obtaining the higher sustained performance and lower energy consumption. Recently, three-dimensional (3D) die stacking technology has attracted much attention to be able to relax several limitations of conventional processor design. Hence, this paper explores the design space of vector processors with a large on-chip memory by using the 3D die stacking technology. A processor design proposed in this paper achieves a 32 MB on-chip memory by stacking four memory layers onto a vector processor layer using the 3D die stacking technology. In addition, an optimal 3D on-chip memory configuration is discussed in this paper. The on-chip memory can reduce the number of off-chip main memory accesses, resulting in higher performance and lower energy consumption of a memory system. Simulation results show that the proposed vector processor can achieve a 55% higher performance and 40% lower energy consumption than a conventional vector processor.