Correlation of PDN Impedance between Measurements and Simulation of 3D-SiP

被引：0

作者：

Kawaguchi, Shohei ^{[1
]}

Sato, Masaomi ^{[1
]}

Takatani, Hiroki ^{[1
]}

Tanaka, Yosuke ^{[1
]}

Fujita, Haruya ^{[1
]}

Suto, Yoichi ^{[1
]}

Sudo, Toshio ^{[1
]}

机构：

[1] Shibaura Inst Technol, Koto Ku, Tokyo 108, Japan

来源：

2013 IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS SYMPOSIUM (EDAPS) | 2013年

关键词：

3D-SiP; ultra-wide bus; simultaneous switching noise; measurement; on-die capacitance; power distribution network (PDN); SILICON; DESIGN; TSV;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Recently, ultra-wide bus 3D-SiP with TSV's has attracted great attention to achieve energy-saving and high-performance system level module. TSV technology is a new technology of vertical wiring to make shorter than the conventional wire bonding. However, the power supply integrity and signal integrity has become an issue due to the increase of simultaneous switching output buffers. In this paper, PDN impedances of 3D-SiP were examined by the measurement and simulation. Simulated PDN impedances of three chips were well correlated with the measured results.

引用

页码：158 / 161

页数：4

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