A Novel Transformer Network and Its Analysis for Power Combiner Blocks in CMOS Technology

被引：0

作者：

Javidan, Javad ^{[1
]}

Torkzadeh, Pooya ^{[1
]}

Atarodi, Mojtaba ^{[1
]}

机构：

[1] Sharif U T, EE Dept, SICAS Grp, Tehran, Iran

来源：

2008 INTERNATIONAL CONFERENCE ON MICROELECTRONICS | 2008年

关键词：

Power amplifier; power combiner; transformer; efficiency optimization;

D O I：

10.1109/ICM.2008.5393523

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, a novel multi-transformer architecture as power combiner for fully integrated CMOS power amplifier will be presented. Proposed transformers are composed of multiple single-turn inductors inside each other to obtain high quality factor and save the area at the same time. According to two proposed and explained topologies for power stages, each transformer network's performance is fully analyzed and has been optimized for obtaining high efficiency versus physical dimensions. Designed transformer networks are optimized for the frequency band of 900MHz using 0.18-mu m TSMC technology.

引用

页码：313 / 316

页数：4

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