CMOS transceiver with baud rate clock recovery for optical interconnects

被引：20

作者：

Emami-Neyestanak, A ^{[1
]}

Palermo, S ^{[1
]}

Lee, HC ^{[1
]}

Horowitz, M ^{[1
]}

机构：

[1] Stanford Univ, Comp Syst Lab, Stanford, CA 94305 USA

来源：

2004 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2004年

关键词：

optical interconnects; clock and data recovery; integrating receiver; 1/0; double sampling; baud rate; VCSEL;

D O I：

10.1109/VLSIC.2004.1346633

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

An efficient baud rate clock and data recovery architecture is applied to a double sampling/integrating front-end receiver for optical interconnects. Receiver performance is analyzed and projected for future technologies. This front-end allows use of a 1:5 demux architecture to achieve 5Gb/s in a 0.25mum CMOS process. A 5:1 multiplexing transmitter is used to drive VCSELs for optical transmission. The transceiver chip consumes 145mW per link at 5Gb/s with a 2.5V supply.

引用

页码：410 / 413

页数：4

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