Effective Transactional Memory Execution Management for Improved Concurrency

被引:9
作者
Gonzalez-Mesa, M. A. [1 ]
Gutierrez, Eladio [1 ]
Zapata, Emilio L. [1 ]
Plata, Oscar [1 ]
机构
[1] Univ Malaga, Dept Comp Architecture, E-29071 Malaga, Spain
关键词
Design; Experimentation; Performance; Transactional memory; concurrency exploitation; dependence analysis; optimistic concurrency; program parallelization;
D O I
10.1145/2633048
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This article describes a transactional memory execution model intended to exploit maximum parallelism from sequential and multithreaded programs. A program code section is partitioned into chunks that will be mapped onto threads and executed transactionally. These transactions run concurrently and out of order, trying to exploit maximum parallelism but managed by a specific fully distributed commit control to meet data dependencies. To accomplish correct parallel execution, a partial precedence order relation is derived from the program code section and/or defined by the programmer. When a conflict between chunks is eagerly detected, the precedence order relation is used to determine the best policy to solve the conflict that preserves the precedence order while maximizing concurrency. The model defines a new transactional state called executed but not committed. This state allows exploiting concurrency on two levels: intrathread and interthread. Intrathread concurrency is improved by having pending uncommitted transactions while executing a new one in the same thread. The new state improves interthread concurrency because it permits out-of-order transaction commits regarding the precedence order. Our model has been implemented in a lightweight software transactional memory system, TinySTM, and has been evaluated on a set of benchmarks obtaining an important performance improvement over the baseline TM system.
引用
收藏
页码:23 / 49
页数:27
相关论文
共 33 条
[1]  
Angel Gonzalez-Mesa M., 2012, 16 WORKSH COMP PAR C
[2]  
[Anonymous], 2008, IEEE INT S WORKL CHA
[3]  
Ansari M, 2008, LECT NOTES COMPUT SC, V5168, P719, DOI 10.1007/978-3-540-85451-7_77
[4]  
Aydonat Utku, 2010, Proceedings 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2010), P15, DOI 10.1109/MICRO.2010.25
[5]  
Baek W., 2007, P 16 INT C PAR ARCH, P376
[6]  
Barreto Joao, 2012, Middleware 2012. ACM/IFIP/USENIX 13th International Middleware Conference. Proceedings, P187, DOI 10.1007/978-3-642-35170-9_10
[7]   The PARSEC Benchmark Suite: Characterization and Architectural Implications [J].
Bienia, Christian ;
Kumar, Sanjeev ;
Singh, Jaswinder Pal ;
Li, Kai .
PACT'08: PROCEEDINGS OF THE SEVENTEENTH INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES, 2008, :72-81
[8]   Transactional Memory for Unstructured Mesh Simulations [J].
Bihari, Barna L. .
JOURNAL OF SCIENTIFIC COMPUTING, 2013, 54 (2-3) :311-332
[9]  
Boisvert RF, 1997, QUALITY OF NUMERICAL SOFTWARE - ASSESSMENT AND ENHANCEMENT, P125
[10]   Automatic code generation and tuning for stencil kernels on modern shared memory architectures [J].
Christen, Matthias ;
Schenk, Olaf ;
Burkhart, Helmar .
COMPUTER SCIENCE-RESEARCH AND DEVELOPMENT, 2011, 26 (3-4) :205-210