7nm Chip-Package Interaction Study on a Fine Pitch Flip Chip Package With Laser Assist Bonding and Mass Reflow Technology

Due to the rapid growth in new technological features in mobile applications, new packaging solutions smaller form factor package designs, lower power consumption and other efficiency enhancements are required for the 7nm node silicon devices. Flip chip technology such as fcCSP (flip chip Chip Scale Package) has been widely adopted as the primary (or preferred) solution for mobile devices to satisfy these challenging requirements. The flip chip CSP package offers a cost-effective solution through the combination of Sn/Ag bumped copper (Cu) pillars, the use embedded trace substrate (ETS) technology along with mass reflow chip attach and molded underfill (MUF) processes.. While mass reflow chip attach process provides a cost-effective solution for flip chip assembly, there is nonetheless a high risk of bump to trace shorting especially as the need increases for finer bump pitch designs, with reduced copper line width and line spacing (LW/LS) for the escaped traces. To reduce this risk, we are exploring the use of laser assisted bonding (LAB) methodology to study the 7nm chip-package interaction (CPI) of a fcCSP with a 60 mu m bump pitch and escaped trace designs in this paper. For the purpose of measuring the extremely low-k (ELK) performance in a 14x14mm fine pitch fcCSP with 7nm node silicon live die, the thunder test, two-times mass reflow followed by a quick temperature cycling (QTC), and the hammer test, a multi-reflow process with a peak temperature of 260 degrees C have been utilized. The results show that although both chip attach methodologies can pass the normal requirements of the thunder and hammer tests, the utilization of LAB technology can further enhance the strength of ELK, resulting in better yield performance. From these results, we believe that LAB not only can guarantee assembly yield but also ensure less ELK damage risk in the evaluated 7nm node silicon fcCSP. Futhermore we have shown that LAB technology is suitable for the 7nm node silicon devices along with the bump pitch reduction using finer LW/LS substrate with escaped traces design.