A Logic Resistive Memory Chip for Embedded Key Storage With Physical Security

被引:22
作者
Xie, Yufeng [1 ,2 ]
Xue, Xiaoyong [1 ,2 ]
Yang, Jianguo [1 ,2 ]
Lin, Yinyin [1 ,2 ]
Zou, Qingtian [3 ]
Huang, Ryan [3 ]
Wu, Jingang [3 ]
机构
[1] Fudan Univ, Sch Microelect, ASIC, Shanghai 201203, Peoples R China
[2] Fudan Univ, Sch Microelect, Syst State Key Lab, Shanghai 201203, Peoples R China
[3] Semicond Mfg Int Corp, Technol Dev Ctr, Shanghai 201203, Peoples R China
基金
中国国家自然科学基金; 美国国家科学基金会;
关键词
Key storage; nonvolatile memory (NVM); resistive random access memory (RRAM); secure memory; SCHEME;
D O I
10.1109/TCSII.2015.2503707
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A 64-kB logic resistive random access memory (RRAM) chip for physically secure key storage is presented. The chip has security features of resisting fully invasive attacks such as deprocessing and microscopy observation, resisting side-channel attacks by providing symmetrical power and timing read signals, resisting malicious writing by a reduced write protection scheme with feedback, and resisting data interception attack across pin boundary by the ability of on-chip integration with logic platform. The chip is fabricated in a 0.13-mu m standard logic process and implemented as the key storage for a demonstrative information security platform with a MIPS-based cryptoprocessor. Experiments of reverse engineering and mechanism investigation proved the fully invasive attack-resistant features, and experiments emulating side-channel attacks revealed no difference between 0 and 1. Experiments also showed that the information security platform could correctly encrypt and decrypt with the RRAM key storage. The proposed chip has obvious advantage on area, power, and security features for embedded key storage compared with its Antifuse counterpart.
引用
收藏
页码:336 / 340
页数:5
相关论文
共 11 条
[1]  
[Anonymous], XPM OTP NVM
[2]  
[Anonymous], SEL TOP SIGNAL PROCE
[3]   Area-Efficient Embedded Resistive RAM ( ReRAM) Macros Using Logic-Process Vertical-Parasitic-BJT ( VPBJT) Switches and Read-Disturb-Free Temperature-Aware Current-Mode Read Scheme [J].
Chang, Meng-Fan ;
Kuo, Chia-Chen ;
Sheu, Shyh-Shyuan ;
Lin, Chorng-Jung ;
King, Ya-Chin ;
Chen, Frederick T. ;
Ku, Tzu-Kun ;
Tsai, Ming-Jinn ;
Wu, Jui-Jen ;
Chih, Yue-Der .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2014, 49 (04) :908-916
[4]  
Helfmeier C., 2014, 2014 Design, Automation Test in Europe Conference Exhibition (DATE), P1, DOI DOI 10.7873/DATE.2014.363
[5]  
Peng J., 2006, P 21 IEEE NVSMW, P24
[6]  
Sadeghi Ahmad-Reza., 2010, HARDWARE INTRINSIC S, DOI 10.1007/978-3-642-14452-3
[7]   A Logic-Compatible Embedded Flash Memory for Zero-Standby Power System-on-Chips Featuring a Multi-Story High Voltage Switch and a Selective Refresh Scheme [J].
Song, Seung-Hwan ;
Chun, Ki Chul ;
Kim, Chris H. .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2013, 48 (05) :1302-1314
[8]   A Novel CuxSiyO Resistive Memory in Logic Technology with Excellent Data Retention and Resistance Distribution for Embedded Applications [J].
Wang, M. ;
Luo, W. J. ;
Wang, Y. L. ;
Yang, L. M. ;
Zhu, W. ;
Zhou, P. ;
Yang, J. H. ;
Gong, X. G. ;
Lin, Y. Y. ;
Huang, R. ;
Song, S. ;
Zhou, Q. T. ;
Wu, H. M. ;
Wu, J. G. ;
Chi, M. H. .
2010 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2010, :89-+
[9]   Algorithm-Enhanced Retention Based on Megabit Array of CuxSiyO RRAM [J].
Wang, Yan-Liang ;
Song, Ya-Li ;
Yang, Ling-Ming ;
Lin, Yin-Yin ;
Huang, Ryan ;
Zou, Qin-Tian ;
Wu, Jin-Gang .
IEEE ELECTRON DEVICE LETTERS, 2012, 33 (10) :1408-1410
[10]   Phase-Change and Redox-Based Resistive Switching Memories [J].
Wouters, Dirk J. ;
Waser, Rainer ;
Wuttig, Matthias .
PROCEEDINGS OF THE IEEE, 2015, 103 (08) :1274-1288