Modeling of High-Performance p-Type IIIV Heterojunction Tunnel FETs

被引:188
作者
Knoch, Joachim [1 ]
Appenzeller, Joerg [2 ]
机构
[1] TU Dortmund Univ, D-44227 Dortmund, Germany
[2] Purdue Univ, Sch Elect & Comp Engn, W Lafayette, IN 47907 USA
关键词
Heterojunctions; MOS devices; tunnel; transistors; FIELD-EFFECT TRANSISTORS; DEVICE DESIGN;
D O I
10.1109/LED.2010.2041180
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The impact of band lineup and source doping concentration on the performance of heterojunction tunnel FETs (H-TFETs) with type-II heterointerface is investigated by simulations. Exemplarily, H-TFETs based on InAs/Al x Ga(1-x) Sb heterostructures are studied. Varying the Al content x, the band lineup can be adjusted from staggered to broken. We find that a staggered band lineup and a medium source doping concentration yield the best ON/OFF-state performance in terms of an inverse subthreshold slope that is smaller than 60 mV/dec and f(T) values in the terahertz range.
引用
收藏
页码:305 / 307
页数:3
相关论文
共 17 条
  • [1] MODULATION-SPECTROSCOPY STUDY OF THE GA1-XALXSB BAND-STRUCTURE
    ALIBERT, C
    JOULLIE, A
    JOULLIE, AM
    ANCE, C
    [J]. PHYSICAL REVIEW B, 1983, 27 (08): : 4946 - 4954
  • [2] Comparing carbon nanotube transistors - The ideal choice: A novel tunneling device design
    Appenzeller, J
    Lin, YM
    Knoch, J
    Chen, ZH
    Avouris, P
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2005, 52 (12) : 2568 - 2576
  • [3] Toward Nanowire Electronics
    Appenzeller, Joerg
    Knoch, Joachim
    Bjoerk, Mikael I.
    Riel, Heike
    Schmid, Heinz
    Riess, Walter
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2008, 55 (11) : 2827 - 2845
  • [4] FABRICATION OF NANOSTRUCTURES IN ALGASB INAS USING ELECTRON-BEAM LITHOGRAPHY AND CHEMICALLY ASSISTED ION-BEAM ETCHING
    ARAFA, M
    YOUTSEY, C
    GRUNDBACHER, R
    ADESIDA, I
    KLEM, J
    [J]. JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 1994, 12 (06): : 3623 - 3625
  • [5] Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's
    Auth, CP
    Plummer, JD
    [J]. IEEE ELECTRON DEVICE LETTERS, 1997, 18 (02) : 74 - 76
  • [6] P-channel tunnel field-effect transistors down to sub-50 nm channel lengths
    Bhuwalka, KK
    Born, M
    Schindler, M
    Schmidt, M
    Sulima, T
    Eisele, I
    [J]. JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 2006, 45 (4B): : 3106 - 3109
  • [7] Performance enhancement of vertical tunnel field-effect transistor with SiGe in the δp+ layer
    Bhuwalka, KK
    Schulze, J
    Eisele, T
    [J]. JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 2004, 43 (7A): : 4073 - 4078
  • [8] Double-gate tunnel FET with high-κ gate dielectric
    Boucart, Kathy
    Mihai Ionescu, Adrian
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2007, 54 (07) : 1725 - 1733
  • [9] Organic-inorganic hybrid materials as solution processible gate insulator for organic thin film transistors
    Choi, Chaun Gi
    Bae, Byeong-Soo
    [J]. ORGANIC ELECTRONICS, 2007, 8 (06) : 743 - 748
  • [10] Optimizing Tunnel FET Performance - Impact of Device Structure, Transistor Dimensions and Choice of Material
    Knoch, Joachim
    [J]. PROCEEDINGS OF TECHNICAL PROGRAM: 2009 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATIONS, 2009, : 45 - 46