A Scalable 3D Processor by Homogeneous Chip Stacking with Inductive-Coupling Link

被引：0

作者：

Kohama, Yoshinori ^{[1
]}

Sugimori, Yasufumi ^{[1
]}

Saito, Shotaro ^{[1
]}

Hasegawa, Yohei ^{[1
]}

Sano, Toru ^{[1
]}

Kasuga, Kazutaka ^{[1
]}

Yoshida, Yoichi ^{[1
]}

Niitsu, Kiichi ^{[1
]}

Miura, Noriyuki ^{[1
]}

Amano, Hideharu ^{[1
]}

Kuroda, Tadahiro ^{[1
]}

机构：

[1] Keio Univ, Dept Elect Engn & Elect, Yokohama, Kanagawa 223, Japan

来源：

2009 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2009年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents homogeneous chip stacking to construct a scalable three-dimensional (3D) processor for the first time. Chips are connected by an inductive-coupling link. Power supply is delivered by conventional wire bonding. A prototype is developed by stacking four dynamically reconfigurable processor (DRP) chips in 90nm CMOS. Active Si area for the vertical link at 7.2Gb/s/chip is 0.031 mm(2). Average execution time is reduced to 31% compared to that using one chip.

引用

页码：94 / 95

页数：2

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