A Scalable 3D Processor by Homogeneous Chip Stacking with Inductive-Coupling Link

被引：0

作者：

Kohama, Yoshinori ^{[1
]}

Sugimori, Yasufumi ^{[1
]}

Saito, Shotaro ^{[1
]}

Hasegawa, Yohei ^{[1
]}

Sano, Toru ^{[1
]}

Kasuga, Kazutaka ^{[1
]}

Yoshida, Yoichi ^{[1
]}

Niitsu, Kiichi ^{[1
]}

Miura, Noriyuki ^{[1
]}

Amano, Hideharu ^{[1
]}

Kuroda, Tadahiro ^{[1
]}

机构：

[1] Keio Univ, Dept Elect Engn & Elect, Yokohama, Kanagawa 223, Japan

来源：

2009 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2009年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents homogeneous chip stacking to construct a scalable three-dimensional (3D) processor for the first time. Chips are connected by an inductive-coupling link. Power supply is delivered by conventional wire bonding. A prototype is developed by stacking four dynamically reconfigurable processor (DRP) chips in 90nm CMOS. Active Si area for the vertical link at 7.2Gb/s/chip is 0.031 mm(2). Average execution time is reduced to 31% compared to that using one chip.

引用

页码：94 / 95

页数：2

共 50 条

[1] MUCCRA-CUBE: A 3D DYNAMICALLY RECONFIGURABLE PROCESSOR WITH INDUCTIVE-COUPLING LINK
Saito, S.
Kohama, Y.
Sugimori, Y.
Hasegawa, Y.
Matsutani, H.
Sano, T.
Kasuga, K.
Yoshida, Y.
Niitsu, K.
Miura, N.
Kuroda, T.
Amano, H.
FPL: 2009 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS, 2009, : 6 - 11
[2] A Scalable 3D Heterogeneous Multi-Core Processor with Inductive-Coupling ThruChip Interface
Miura, Noriyuki
Koizumi, Yusuke
Sasaki, Eiichi
Take, Yasuhiro
Matsutani, Hiroki
Kuroda, Tadahiro
Amano, Hideharu
Sakamoto, Ryuichi
Namiki, Mitaro
Usami, Kimiyoshi
Kondo, Masaaki
Nakamura, Hiroshi
2013 IEEE COOL CHIPS XVI (COOL CHIPS), 2013,
[3] Inductive-coupling transceiver for 3D system integration
Miura, Noriyuki
Kuroda, Tadahiro
2007 IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUIT DESIGN AND TECHNOLOGY, PROCEEDINGS, 2007, : 172 - +
[4] 3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link
Saen, Makoto
Osada, Kenichi
Okuma, Yasuyuki
Niitsu, Kiichi
Shimazaki, Yasuhisa
Sugimori, Yasufumi
Kohama, Yoshinori
Kasuga, Kazutaka
Nonomura, Itaru
Irie, Naohiko
Hattori, Toshihiro
Hasegawa, Atsushi
Kuroda, Tadahiro
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2010, 45 (04) : 856 - 862
[5] An Inductive-Coupling Link for 3-D Network-on-Chips
Kadomoto, Junichiro
Amano, Hideharu
Kuroda, Tadahiro
PROCEEDINGS INTERNATIONAL SOC DESIGN CONFERENCE 2017 (ISOCC 2017), 2017, : 150 - 151
[6] 3D System Integration of Processor and Multi-Stacked SRAMs by Using Inductive-Coupling Links
Osada, Kenichi
Saen, Makoto
Okuma, Yasuyuki
Niitsu, Kiichi
Shimazaki, Yasuhisa
Sugimori, Yasufumi
Kohama, Yoshinori
Kasuga, Kazutaka
Nonomura, Itaru
Irie, Naohiko
Hattori, Toshihiro
Hasegawa, Atsushi
Kuroda, Tadahiro
2009 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2009, : 256 - +
[7] A single phase modulation for pulse-based inductive-coupling connection in 3D stacked chip
Zhang, Li
Xu, Xiaowei
Li, Dawei
Chen, Xiaofei
Zou, Xuecheng
IEICE ELECTRONICS EXPRESS, 2017, 14 (20):
[8] A 50% power reduction in inductive-coupling transceiver for 3D-stacked inter-chip data link
Zhang, Li
Li, Tie
Wang, Baocun
Zou, Xuecheng
7TH IEEE INTERNATIONAL NANOELECTRONICS CONFERENCE (INEC) 2016, 2016,
[9] A Wafer Test Method of Inductive-Coupling Link
Kasuga, Kazutaka
Saito, Mitsuko
Takeya, Tsutomu
Miura, Noriyuki
Ishikuro, Hiroki
Kuroda, Tadahiro
2009 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC), 2009, : 301 - 304
[10] 3D NoC with Inductive-Coupling Links for Building-Block SiPs
Take, Yasuhiro
Matsutani, Hiroki
Sasaki, Daisuke
Koibuchi, Michihiro
Kuroda, Tadahiro
Amano, Hideharu
IEEE TRANSACTIONS ON COMPUTERS, 2014, 63 (03) : 748 - 763

← 1 2 3 4 5 →