On-chip global signaling by wave pipelining

被引：9

作者：

Hashimoto, M ^{[1
]}

Tsuchiya, A ^{[1
]}

Onodera, H ^{[1
]}

机构：

[1] Osaka Univ, Dept ISE, Suita, Osaka 5650871, Japan

来源：

ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING | 2004年

关键词：

D O I：

10.1109/EPEP.2004.1407619

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper discusses the signaling performance of wave pipelining over on-chip transmission lines comparing conventional signaling with CMOS static repeater insertion. We experimentally reveal that the wave pipelining over on-chip transmission lines is about ten times superior in the maximum throughput, latency and dissipates several times less energy per bit compared with the conventional signaling, whereas the required interconnect resource is comparable.

引用

页码：311 / 314

页数：4

共 16 条

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[2]

Dally W, 2008, DIGITAL SYSTEMS ENG

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