VHDL Implementation of Low-Power Turbo Decoder

被引：0
|
作者：
Vijyata [1 ]
Meena, R. S. [1 ]
Sharma, J. B. [1 ]
机构：
[1] Rajasthan Tech Univ, Dept Elect Engn, Kota, India
来源：
2016 IEEE UTTAR PRADESH SECTION INTERNATIONAL CONFERENCE ON ELECTRICAL, COMPUTER AND ELECTRONICS ENGINEERING (UPCON) | 2016年
关键词：
log-map algorithm; LLR; BMC; ACS; BSMC; FSMC; VHDL; DESIGN;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Due to famous mistake revising probability turbo coding is significantly used as a piece of advanced correspondence systems. In this paper different arrangement of turbo decoder with decreased element constrain dissemination is shown. In this changed decoder, standard cell based design using pipeline logarithm-most extreme a back (Log-MAP) calculation with clock gating and variable number of cycle is used to reduce the territory and to expand the throughput. Proposed design of modified log-outline decoder is mimicked and mixes using Xilinx14.2. Outcomes of the proposed low-control balanced log-MAP decoder are better than the customary log-MAP turbo decoder.
引用
收藏
页码：602 / 607
页数：6
相关论文
共 50 条
  • [31] Low-Power Memory-Reduced Traceback MAP Decoding for Double-Binary Convolutional Turbo Decoder
    Lin, Cheng-Hung
    Chen, Chun-Yu
    Wu, An-Yeu
    Tsai, Tsung-Han
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2009, 56 (05) : 1005 - 1016
  • [32] Power and area efficient turbo decoder implementation for mobile wireless systems
    Han, JH
    Erdogan, AT
    Arslan, T
    2005 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS - DESIGN AND IMPLEMENTATION (SIPS), 2005, : 705 - 709
  • [33] Design and Implementation of Viterbi Decoder Using VHDL
    Thakur, Akash
    Chattopadhyay, Manju K.
    3RD INTERNATIONAL CONFERENCE ON COMMUNICATION SYSTEMS (ICCS-2017), 2018, 331
  • [34] Block processing technique for low power turbo decoder design
    Lee, I
    Vallejo, ML
    Mujtaba, SA
    IEEE 55TH VEHICULAR TECHNOLOGY CONFERENCE, VTC SPRING 2002, VOLS 1-4, PROCEEDINGS, 2002, : 1025 - 1029
  • [35] Implementation and performance of a turbo/MAP decoder
    Pietrobon, SS
    INTERNATIONAL JOURNAL OF SATELLITE COMMUNICATIONS, 1998, 16 (01): : 23 - 46
  • [36] Implementation of Turbo/MAP decoder hardware
    Wang, Xue-Dong
    Yang, Hua
    Harbin Gongye Daxue Xuebao/Journal of Harbin Institute of Technology, 2002, 34 (02): : 173 - 176
  • [37] FPGA design and implementation of a low-power Systolic array-based adaptive viterbi decoder
    Guo, M
    Ahmad, MO
    Swamy, MNS
    Wang, CY
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2005, 52 (02) : 350 - 365
  • [38] A low-power systolic array-based adaptive Viterbi decoder and its FPGA implementation
    Guo, M
    Ahmad, MO
    Swamy, MNS
    Wang, CY
    PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II: COMMUNICATIONS-MULTIMEDIA SYSTEMS & APPLICATIONS, 2003, : 276 - 279
  • [39] A low-power VLSI implementation for variable length decoder in MPEG-1 layer III
    Tsai, TH
    Liu, CN
    Chen, WC
    EMBEDDED PROCESSORS FOR MULTIMEDIA AND COMMUNICATIONS, 2004, 5309 : 30 - 39
  • [40] A low-power H.264/AVC decoder
    Lin, TA
    Liu, TM
    Lee, CY
    2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation & Test (VLSI-TSA-DAT), Proceedings of Technical Papers, 2005, : 283 - 286
12345