VHDL Implementation of Low-Power Turbo Decoder

被引：0
|
作者：
Vijyata [1 ]
Meena, R. S. [1 ]
Sharma, J. B. [1 ]
机构：
[1] Rajasthan Tech Univ, Dept Elect Engn, Kota, India
来源：
2016 IEEE UTTAR PRADESH SECTION INTERNATIONAL CONFERENCE ON ELECTRICAL, COMPUTER AND ELECTRONICS ENGINEERING (UPCON) | 2016年
关键词：
log-map algorithm; LLR; BMC; ACS; BSMC; FSMC; VHDL; DESIGN;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Due to famous mistake revising probability turbo coding is significantly used as a piece of advanced correspondence systems. In this paper different arrangement of turbo decoder with decreased element constrain dissemination is shown. In this changed decoder, standard cell based design using pipeline logarithm-most extreme a back (Log-MAP) calculation with clock gating and variable number of cycle is used to reduce the territory and to expand the throughput. Proposed design of modified log-outline decoder is mimicked and mixes using Xilinx14.2. Outcomes of the proposed low-control balanced log-MAP decoder are better than the customary log-MAP turbo decoder.
引用
收藏
页码：602 / 607
页数：6
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