Monolithic Three-Dimensional 65-nm CMOS-Nanoelectromechanical Reconfigurable Logic for Sub-1.2-V Operation

被引：33

作者：

Kwon, Hyug Su ^{[1
]}

Kim, Seung Kyu ^{[1
]}

Choi, Woo Young ^{[1
]}

机构：

[1] Sogang Univ, Dept Elect Engn, Seoul 04107, South Korea

来源：

IEEE ELECTRON DEVICE LETTERS | 2017年 / 38卷 / 09期

基金：

新加坡国家研究基金会;

关键词：

CMOS; nanoelectromechanical (NEM) memory switch; monolithic three-dimensional (M3D) integration; reconfigurable logic (RL) circuit;

D O I：

10.1109/LED.2017.2726685

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Monolithic three-dimensional (M3D) CMOS-nanoelectromechanical (CMOS-NEM) reconfigurable logic (RL) circuits are experimentally demonstrated. This is the first experimental demonstration of 65-nm M3D CMOS-NEM RL circuits satisfying the 1.2-V supply voltage (VDD) requirement of the 65-nm technology node. The fabrication process is identical to the conventional 65-nm CMOS baseline process, in which copper NEM memory switches are formed by a dual damascene process.

引用

页码：1317 / 1320

页数：4

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