90 nm generation, 300mm wafer low k ILD/Cu interconnect technology

被引：22

作者：

Jan, CH ^{[1
]}

Bielefeld, J ^{[1
]}

Buehler, M ^{[1
]}

Chikamane, V ^{[1
]}

Fischer, K ^{[1
]}

Hepburn, T ^{[1
]}

Jain, A ^{[1
]}

Jeong, J ^{[1
]}

Kielty, T ^{[1
]}

Kook, S ^{[1
]}

Marieb, T ^{[1
]}

Miner, B ^{[1
]}

Nguyen, P ^{[1
]}

Schmitz, A ^{[1
]}

Nashner, M ^{[1
]}

Scherban, T ^{[1
]}

Schroeder, B ^{[1
]}

Wang, PH ^{[1
]}

Wu, R ^{[1
]}

Xu, J ^{[1
]}

Zawadzki, K ^{[1
]}

Thompson, S ^{[1
]}

Bohr, M ^{[1
]}

机构：

[1] Intel Corp, Log Technol Dev, Hillsboro, OR USA

来源：

PROCEEDINGS OF THE IEEE 2003 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE | 2003年

关键词：

D O I：

10.1109/IITC.2003.1219699

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a 90 nm generation and 300 mm wafer size interconnect technology with 7 layers of Cu metallization and low k ILD. Carbon doped oxide (CDO) low k ILD is used to achieve > 20% inter- and intra-layer capacitance improvement and 25-30% RC improvement over 130 nm generation SiOF interconnect process with equivalent electro-migration performance.

引用

页码：15 / 17

页数：3

共 3 条

[1]

Thompson S, 2002, INTERNATIONAL ELECTRON DEVICES 2002 MEETING, TECHNICAL DIGEST, P61, DOI 10.1109/IEDM.2002.1175779

[2]

TYAGI S, 2000, IEDM, P561

[3] A high performance 180 nm generation logic technology [J].

Yang, S ;

Ahmed, S ;

Arcot, B ;

Arghavani, R ;

Bai, P ;

Chambers, S ;

Charvat, P ;

Cotner, R ;

Gasser, R ;

Ghani, T ;

Hussein, M ;

Jan, C ;

Kardas, C ;

Maiz, J ;

McGregor, F ;

McIntyre, B ;

Nguyen, P ;

Packan, P ;

Post, I ;

Sivakumar, S ;

Steigerwald, J ;

Taylor, M ;

Tufts, B ;

Tyagi, S ;

Bohr, M .

INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST, 1998, :197-200

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