Low power scheduling of DAGs to minimize finish times

We propose a schedule named Low Power Heterogeneous Makespan (LPHM) that attempts to minimize makespan as well as power consumption in the execution of any directed acyclic task graph on heterogeneous processors. We combine the techniques of Heterogeneous Earliest Finish Time (HEFT) [9] and voltage scaling [4]. The processors used for execution are considered to be continuously voltage scalable within the range of operation. After initial scheduling for minimum makespan, the processors are voltage scaled down to reduce power consumption whenever there is an idle time. This voltage scaling is performed without violating the precedence relationships among tasks. The simulation results show power savings of 22% over HEFT with no increase in makespan.