A four-channel ADSL2+ analog front-end for CO applications with 75 mW per channel, built in 0.13-μm CMOS

被引：5

作者：

Pessl, P ^{[1
]}

Gaggl, R ^{[1
]}

Hohl, J ^{[1
]}

Giotta, D ^{[1
]}

Hauptmann, J ^{[1
]}

机构：

[1] Infineon Technol Design Ctr Austria, A-9500 Villach, Austria

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2004年 / 39卷 / 12期

关键词：

ADSL; analog front-end (AFE);

D O I：

10.1109/JSSC.2004.835645

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes a four-channel ADSL2+ analog front-end (AFE) targeted at a central office application, with a power consumption of 75 mW per channel. The design is implemented using a modern 0.13-mum CMOS process. The AFE consists of a 14-bit ADC and DAC, a very low-noise high-linearity automatic gain control (AGC), analog filter blocks, and digital decimation and interpolation filter stages. The design has been optimized to achieve the lowest possible power consumption, high performance, and cost efficiency.

引用

页码：2371 / 2378

页数：8

共 9 条

[1] Linearity enhancement of multibit Delta Sigma and D/A converters using data weighted averaging [J].

Baird, RT ;

Fiez, TS .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 1995, 42 (12) :753-762

[2] On the jitter requirements of the sampling clock for analog-to-digital converters [J].

Da Dalt, N ;

Harteneck, M ;

Sandner, C ;

Wiesbauer, A .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS, 2002, 49 (09) :1354-1360

[3] A 85-dB dynamic range multibit delta-sigma ADC for ADSL-CO applications in 0.18-/-μm CMOS [J].

Gaggl, R ;

Wiesbauer, A ;

Fritz, G ;

Schranz, C ;

Pessl, P .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2003, 38 (07) :1105-1114

[4] CODEC for echo-canceling, full-rate ADSL modems [J].

Hester, RK ;

Padgett, D ;

Richardson, D ;

Bright, W ;

Sarraj, MM ;

Nabicht, JT ;

Agah, MD ;

Bellaouar, A ;

Chaudhry, I ;

Hellums, JR ;

Islam, K ;

Loloee, A ;

Tsay, CY ;

Westphal, G .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1999, 34 (12) :1973-1985

[5]

JOHNS DA, 1997, ANALOG INTEGRATED CI

[6]

KOKOZINSKI R, 2000, P 26 ESSCIRC SEP, P452

[7] A BiCMOS analog front-end circuit for an FDM-based ADSL system [J].

Langford, DS ;

Tesch, BJ ;

Williams, BE ;

Nelson, GR .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1998, 33 (09) :1383-1393

[8] A CMOS ADSL codec for central office applications [J].

Siniscalchi, PP ;

Pitz, JK ;

Hester, RK ;

DeSoto, SM ;

Wang, MS ;

Sridharan, S ;

Halbach, RL ;

Richardson, D ;

Bright, W ;

Sarraj, MM ;

Hellums, JR ;

Betty, CL ;

Westphal, G .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2001, 36 (03) :356-365

[9]

STEYAERT M, 2002, ANALOG CIRCUIT DESIG, P261

← 1 →