Vertical floating-gate 4.5F2 split-gate NOR flash memory at 110nm node

被引：0

作者：

Lee, D ^{[1
]}

Tsui, F ^{[1
]}

Yang, JW ^{[1
]}

Gao, F ^{[1
]}

Lu, WJ ^{[1
]}

Lee, Y ^{[1
]}

Chen, CT ^{[1
]}

Huang, V ^{[1
]}

Wang, PY ^{[1
]}

Liu, MH ^{[1
]}

Hsu, HC ^{[1
]}

Chang, S ^{[1
]}

Chang, SY ^{[1
]}

Van Tran, H ^{[1
]}

Frayer, J ^{[1
]}

Hu, YW ^{[1
]}

Yeh, B ^{[1
]}

Chen, B ^{[1
]}

机构：

[1] Silicon Storage Technol Inc, Sunnyvale, CA 94086 USA

来源：

2004 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2004年

关键词：

flash memory; self-aligned; vertical-channel;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We present the structural and electrical characteristics of the latest generation of a self-aligned split-gate NOR memory incorporating a vertical floating-gate channel having 4.5F(2) area on 110nm half-pitch rules. With enhanced electric fields for erase and programming, the cell achieves erase time < 1ms and program time < 10 mus at 100nA programming current. These results demonstrate continued scalability of the SuperFlash cell for high-density, high-speed applications.

引用

页码：72 / 73

页数：2

共 5 条

[1]

CHI MH, 1999, S VLSI TECH, P199

[2]

Choi J.-D., 2001, IEDM, P25

[3]

KEENEY S, 2001, IEDM, P41

[4]

KIANIAN S, 1994, 1994 SYMPOSIUM ON VLSI TECHNOLOGY, P71, DOI 10.1109/VLSIT.1994.324372

[5] 0.18um modular triple self-aligned embedded split-gate flash memory [J].

Mih, R ;

Harrington, J ;

Houlihan, K ;

Lee, HK ;

Chan, K ;

Johnson, J ;

Chen, B ;

Yan, J ;

Schmidt, A ;

Gruensfelder, C ;

Kim, K ;

Shum, D ;

Lo, C ;

Lee, D ;

Levi, A ;

Lam, C .

2000 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2000, :120-121

← 1 →