Receiver adaptation and system characterization of an 8Gbps source-synchronous I/O link using on-die circuits in 0.13μm CMOS

被引：2

作者：

Balamurugan, G ^{[1
]}

Jaussi, J ^{[1
]}

Johnson, DR ^{[1
]}

Casper, B ^{[1
]}

Martin, A ^{[1
]}

Kennedy, J ^{[1
]}

Mooney, R ^{[1
]}

Shanbhag, N ^{[1
]}

机构：

[1] Univ Illinois, Urbana, IL 61801 USA

来源：

2004 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2004年

关键词：

D O I：

10.1109/VLSIC.2004.1346613

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes a 0.13 mum CMOS, 8Gbps I/O receiver that uses on-die circuits for receiver adaptation and system characterization. On-die adaptive control is used to tune a 4-tap receive-side analog equalizer, cancel receiver offsets, and determine optimal sampling phase. Adaptive equalization improves data rates by 1.3x-2x over 2"40" FR4 channels. Noise-margin degradation due to statistical variation in adapted coefficients and offsets is less than 3% of the signal swing. On-die circuits are also used to characterize link performance, channel response, and receiver circuits.

引用

页码：356 / 359

页数：4

共 6 条

[1] Transmitter equalization for 4-Gbps signaling [J].