Low-Power HEVC 1-D IDCT Hardware Architecture

被引：0

作者：

Braatz, Luciano ^{[1
]}

Palomino, Daniel ^{[2
]}

Agostini, Luciano ^{[2
]}

Zatt, Bruno ^{[2
]}

Porto, Marcelo ^{[2
]}

机构：

[1] Fed Univ Pelotas UFPel, Video Technol Res Grp ViTech, Grp Architectures & Integrated Circuits GACI, Pelotas, Brazil

[2] Univ Fed Pelotas, ViTech GACI, Pelotas, Brazil

来源：

2018 31ST SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN (SBCCI) | 2018年

关键词：

video coding; HEVC; inverse transformation; low power;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a low-power (High Efficiency Video Coding) HEVC 1-D IDCT (One-Dimension Inverse Discrete Cosine Transform) hardware architecture, employing a bypass engine to reduce power dissipation. The bypass engine reduces power by replacing the regular 1-D IDCT algorithm by much simpler operations when applicable. Due to an average applicability rate of 87.57%, the low-power HEVC 1-D IDCT can substantially reduce the power dissipation with a slight area overhead. ASIC synthesis results estimates the power dissipation in 3.12 mW when operating at 789.32 MHz. Such frequency is enough to real-time encoding of Ultra-High Definition (UHD 4K) videos at 60 frames per second. Moreover, the presented energy saving hardware architecture can reduce 26% in power dissipation when compared to the regular 1-D IDCT hardware architecture.

引用

页数：6

共 50 条

[11] A Low-Power VLSI Architecture for HEVC De-Quantization and Inverse Transform
Sun, Heming
Zhou, Dajiang
Zhang, Shuping
Kimura, Shinji
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2016, E99A (12): : 2375 - 2387
[12] Low-Power and High-Throughput Architecture for 3D-HEVC Depth Modeling Mode 4
Ucker, Mariana
Afonso, Vladimir
Audibert, Luan
Susin, Altamiro
Zatt, Bruno
Porto, Marcelo
Agostini, Luciano
2018 31ST SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN (SBCCI), 2018,
[13] A Low-Power Hardware Architecture for Real-Time CNN Computing
Liu, Xinyu
Cao, Chenhong
Duan, Shengyu
SENSORS, 2023, 23 (04)
[14] Low-Power Hardware Architecture for Depthwise Separable Convolution Unit Design
Lin, Shi-Rou
Lin, Wei-Hung
Huang, Shih-Hsu
Hsu, Chun-Lung
Sun, Chitien
2020 IEEE INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS - TAIWAN (ICCE-TAIWAN), 2020,
[15] High-Throughput and Low-Power Integrated Direct/Inverse HEVC Quantization Hardware Design
Braatz, Luciano
Zatt, Bruno
Palomino, Daniel
Agostini, Luciano
Porto, Marcelo
2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2018,
[16] High-speed/low-power 1-D DWT architectures with high efficiency
Marino, F
Gevorkian, D
Astola, JT
ISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL V: EMERGING TECHNOLOGIES FOR THE 21ST CENTURY, 2000, : 337 - 340
[17] Low-power HEVC Binarizer Architecture for the CABAC Block targeting UHD Video Processing
Alonso, Camila de Matos
Ramos, Fabio Luis Livi
Zatt, Bruno
Porto, Marcelo
Bampi, Sergio
2017 30TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN (SBCCI 2017): CHOP ON SANDS, 2017, : 30 - 35
[18] Low-Power HEVC 8-point 2-D Discrete Cosine Transform Hardware Using Adder Compressors
Sequeira, Luis F.
Santana, Gustavo M.
Paim, Guilherme
Rocha, Leandro M. G.
Abreu, Brunno
Costa, Eduardo
Bampi, Sergio
2018 16TH IEEE INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS), 2018, : 309 - 312
[19] Novel Low Power, High Speed Hardware Implementation of 1D DCT/IDCT Using Xilinx FPGA
Megalingam, Rajesh Kannan
Sarma, Vineeth V.
Krishnan, Venkat B.
Mithun, M.
Srikumar, Rahul
PROCEEDINGS OF THE 2009 INTERNATIONAL CONFERENCE ON COMPUTER TECHNOLOGY AND DEVELOPMENT, VOL 1, 2009, : 530 - 534
[20] A Low-Complexity Algorithm and Its Low-Power and High-Throughput Architecture for 3D-HEVC DMM-1 Encoding Tool
Borges, Vinicius
Perleberg, Murilo
Afonso, Vladimir
Porto, Marcelo
Agostini, Luciano
2020 IEEE 11TH LATIN AMERICAN SYMPOSIUM ON CIRCUITS & SYSTEMS (LASCAS), 2020,

← 1 2 3 4 5 →