Low-Power HEVC 1-D IDCT Hardware Architecture

This paper presents a low-power (High Efficiency Video Coding) HEVC 1-D IDCT (One-Dimension Inverse Discrete Cosine Transform) hardware architecture, employing a bypass engine to reduce power dissipation. The bypass engine reduces power by replacing the regular 1-D IDCT algorithm by much simpler operations when applicable. Due to an average applicability rate of 87.57%, the low-power HEVC 1-D IDCT can substantially reduce the power dissipation with a slight area overhead. ASIC synthesis results estimates the power dissipation in 3.12 mW when operating at 789.32 MHz. Such frequency is enough to real-time encoding of Ultra-High Definition (UHD 4K) videos at 60 frames per second. Moreover, the presented energy saving hardware architecture can reduce 26% in power dissipation when compared to the regular 1-D IDCT hardware architecture.