An effective distributed BIST architecture for RAMs

被引：16

作者：

Bodoni, ML ^{[1
]}

Benso, A ^{[1
]}

Chiusano, S ^{[1
]}

Di Carlo, S ^{[1
]}

Di Natale, G ^{[1
]}

Prinetto, P ^{[1
]}

机构：

[1] Siemens Informat & Commun Networks SpA, Castelletto Settimo Milanese, I-20019 Milan, Italy

来源：

IEEE EUROPEAN TEST WORKSHOP, PROCEEDINGS | 2000年

关键词：

D O I：

10.1109/ETW.2000.873788

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

The present paper proposes a solution to the problem of testing a system containing many distributed memories of different sizes. The proposed solution relies in the development of a BIST architecture characterized by a sblgle BIST Processor, implemented as a microprogrammable machine and able to execute different test algorithms, a Wrapper for each SRAM including standard memory BIST modules, and an interface block to manage the communications between the SRAM and the BIST Processor Both area overhead and routing costs are minimized, and a scan-based approach allows full diagnostic capabilities of the faults possibly detected in the memories under test.

引用

页码：119 / 124

页数：6