An all-digital phase-locked loop for high-speed clock generation

被引:147
作者
Chung, CC [1 ]
Lee, CY [1 ]
机构
[1] Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu 300, Taiwan
关键词
all-digital phase-locked loop (ADPLL); clock generator; frequency synthesizer; HDL; low jitter;
D O I
10.1109/JSSC.2002.807398
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
An all-digital phase-locked loop (ADPLL) for high-speed clock generation is presented in this brief. The proposed ADPLL architecture uses both a digital control mechanism and a ring oscillator and, hence, can be implemented with standard cells. The ADPLL implemented in a 0.3-mum one-poly-four-metal CMOS process can operate from 45 to 510 MHz and achieve worst case frequency acquisition in 46 reference clock cycles. The power dissipation of the ADPLL is 100 mW (at 500 MHz) with a 3.3-V power supply. From chip measurement results, the P-k-P-k jitter of the output clock is < 70 ps; and the root-mean-square jitter of the output clock is < 22 ps. A systematic way to design the ADPLL with the specified standard cell library is also presented in this brief. The proposed ADPLL can easily be ported to different processes in a short time. Thus, it can reduce the design time and design complexity of the ADPLL, making it very suitable for system-on-chip applications.
引用
收藏
页码:347 / 351
页数:5
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