Optimal termination of on-chip transmission-lines for high-speed signaling

被引：9

作者：

Tsuchiya, Akira ^{[1
]}

Hashimoto, Masanori

Onodera, Hidetoshi

机构：

[1] Kyoto Univ, Dept Commun & Comp Engn, Kyoto 6068501, Japan

[2] Osaka Univ, Dept Informat Syst Engn, Suita, Osaka 5650871, Japan

来源：

IEICE TRANSACTIONS ON ELECTRONICS | 2007年 / E90C卷 / 06期

关键词：

on-chip transmission-line; termination;

D O I：

10.1093/ietele/e90-c.6.1267

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper discusses the resistive termination of on-chip high-performance interconnects. Resistive termination is effective to improve the bandwidth of on-chip interconnects, on the other hands, increases the power dissipation and the area. Therefore trade-off analysis about resistive termination is necessary. This paper proposes a method to determine the termination of on-chip interconnects. The termination derived by the proposed method provides minimum sensitivity to process variation as well as maximum eye-opening in voltage.

引用

页码：1267 / 1273

页数：7

共 6 条

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[Anonymous], 2005, INT TECHN ROADM SEM

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[3]

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[5]

Tsuchiya A, 2003, IEICE T FUND ELECTR, VE86A, P2942

[6] Performance limitation of on-chip global interconnects for high-speed signaling [J].

Tsuchiya, A ;

Hashimoto, M ;

Onodera, H .

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2005, E88A (04) :885-891

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