A 12 Bit Split-Array Switched Capacitor Power Amplifier in 130nm CMOS

被引：0

作者：

Bai, Zhidong ^{[1
]}

Johnson, Dallas ^{[1
]}

Azam, Ali ^{[1
]}

Saha, Anirban ^{[1
]}

Yuan, Wen ^{[1
]}

Walling, Jeffrey S. ^{[1
]}

机构：

[1] Univ Utah, PERFIC Lab, Salt Lake City, UT 84112 USA

来源：

2016 29TH IEEE INTERNATIONAL SYSTEM-ON-CHIP CONFERENCE (SOCC) | 2016年

基金：

美国国家科学基金会;

关键词：

Class-D PA; Digital PA; EER; Switched-Capacitor PA; SCPA; Split Array DAC; DESIGN;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a 12 bit split-array switched-capacitor power amplifier (SA-SCPA) to improve resolution of an SCPA and hence the linear dynamic range. An attenuation capacitor added between two sub-arrays allows a smaller ratio between the smallest and largest capacitors in the array, accommodating better matching. To compromise between efficiency and linearity, 4 binary bits are chosen for the LSB sub-array and 4 binary + 4 unary bits are chosen for the MSB sub-array. The SA-SCPA is designed and extracted, in a 130nm RF CMOS technology. It delivers a peak output power of 22.6dBm with a peak PAE of 30%. The linearity of the array is simulated using a 64 QAM, OFDM signal with 20 MHz bandwidth and the EVM is 3.8% while meeting the spectral mask.

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收藏

页码：24 / 28

页数：5

相关论文

共 12 条

[1] A Fully-Integrated Efficient CMOS Inverse Class-D Power Amplifier for Digital Polar Transmitters [J].

Chowdhury, Debopriyo ;

Thyagarajan, Siva V. ;

Ye, Lu ;

Alon, Elad ;

Niknejad, Ali M. .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2012, 47 (05) :1113-1122

[2]

Cruise P., 2005, DIGITAL TO RF AMPLIT

[3] 500-MS/s 5-bit ADC in 65-nm CMOS with split capacitor array DAC [J].

Ginsburg, Brian P. ;

Chandrakasan, Anantha P. .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2007, 42 (04) :739-747

[4] Analysis and design of high efficiency matching networks [J].

Han, Yehui ;

Perreault, David J. .

IEEE TRANSACTIONS ON POWER ELECTRONICS, 2006, 21 (05) :1484-1491

[5] A Digitally Modulated Polar CMOS Power Amplifier With a 20-MHz Channel Bandwidth [J].

Kavousian, Amirpouya ;

Su, David K. ;

Hekmat, Mohammad ;

Shirvani, Alireza ;

Wooley, Bruce A. .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2008, 43 (10) :2251-2258

[6] Improved binary-weighted split-capacitive-array DAC for high-resolution SAR ADCs [J].

Li, Y. ;

Lian, Y. .

ELECTRONICS LETTERS, 2014, 50 (17) :1194-+

[7] A 25 dBm Digitally Modulated CMOS Power Amplifier for WCDMA/EDGE/OFDM With Adaptive Digital Predistortion and Efficient Power Control [J].

Presti, Calogero D. ;

Carrara, Francesco ;

Scuderi, Antonino ;

Asbeck, Peter M. ;

Palmisano, Giuseppe .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2009, 44 (07) :1883-1896

[8] Design Considerations for a Direct Digitally Modulated WLAN Transmitter With Integrated Phase Path and Dynamic Impedance Modulation [J].

Ye, Lu ;

Chen, Jiashu ;

Kong, Lingkai ;

Alon, Elad ;

Niknejad, Ali M. .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2013, 48 (12) :3160-3177

[9] A Class-G Switched-Capacitor RF Power Amplifier [J].

Yoo, Sang-Min ;

Walling, Jeffrey S. ;

Degani, Ofir ;

Jann, Benjamin ;

Sadhwani, Ram ;

Rudell, Jacques C. ;

Allstot, David J. .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2013, 48 (05) :1212-1224

[10] A Switched-Capacitor RF Power Amplifier [J].

Yoo, Sang-Min ;

Walling, Jeffrey S. ;

Woo, Eum Chan ;

Jann, Benjamin ;

Allstot, David J. .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2011, 46 (12) :2977-2987