A Phase-Locked Loop Based Technique for Accurate Estimation of Grid Voltage Fundamental Parameters

Phase-locked loop based on an anticonjugate decomposition and a cascaded delayed signal cancellation (ACDSC-PLL) strategy is a recognized technique for estimating the single-phase grid voltage fundamental parameters such as amplitude, frequency and phase angle. However, it struggles with high order harmonics and increases complexity in real time implementation when the number of delayed signal cancellation (DSC) operators is increased. To overcome these problems, this paper proposes a technique where the conventional ACDSCPLL is combined with a simple selective filtering stage. The addition of selective filtering makes the proposed technique capable of removing high order harmonics with a dynamic delay slightly greater than one fundamental cycle. When compared to the conventional one, the proposed technique is relatively simple as it needs less number of DSC operators. Simulation results are presented to verify the performance of the proposed technique.